PCI: cadence: Remove "cdns,max-outbound-regions" DT property

"cdns,max-outbound-regions" device tree property provides the
maximum number of outbound regions supported by the Host PCIe
controller. However the outbound regions are configured based
on what is populated in the "ranges" DT property.

Avoid using two properties for configuring outbound regions and
use only "ranges" property instead.

Link: https://lore.kernel.org/r/20200508130646.23939-3-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tom Joseph <tjoseph@cadence.com>

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 9b1c396..e5e9a32 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
        for_each_of_pci_range(&parser, &range) {
                bool is_io;
 
-               if (r >= rc->max_regions)
-                       break;
-
                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
                        is_io = false;
                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
@@ -219,9 +216,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
        pcie = &rc->pcie;
        pcie->is_rc = true;
 
-       rc->max_regions = 32;
-       of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
-
        rc->no_bar_nbits = 32;
        of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
 

diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index a2b28b9..6bd89a2 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -251,7 +251,6 @@ struct cdns_pcie {
  * @bus_range: first/last buses behind the PCIe host controller
  * @cfg_base: IO mapped window to access the PCI configuration space of a
  *            single function at a time
- * @max_regions: maximum number of regions supported by the hardware
  * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
  *                translation (nbits sets into the "no BAR match" register)
  * @vendor_id: PCI vendor ID
@@ -262,7 +261,6 @@ struct cdns_pcie_rc {
        struct resource         *cfg_res;
        struct resource         *bus_range;
        void __iomem            *cfg_base;
-       u32                     max_regions;
        u32                     no_bar_nbits;
        u16                     vendor_id;
        u16                     device_id;