phy: qcom-qmp: move QSERDES registers to separate header

Move QSERDES V2 registers to the separate header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-9-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
new file mode 100644 (file)
index 0000000..9dfa802
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_H_
+#define QCOM_PHY_QMP_QSERDES_COM_H_
+
+/* Only for QMP V2 PHY - QSERDES COM registers */
+#define QSERDES_COM_BG_TIMER                           0x00c
+#define QSERDES_COM_SSC_EN_CENTER                      0x010
+#define QSERDES_COM_SSC_ADJ_PER1                       0x014
+#define QSERDES_COM_SSC_ADJ_PER2                       0x018
+#define QSERDES_COM_SSC_PER1                           0x01c
+#define QSERDES_COM_SSC_PER2                           0x020
+#define QSERDES_COM_SSC_STEP_SIZE1                     0x024
+#define QSERDES_COM_SSC_STEP_SIZE2                     0x028
+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN                        0x034
+#define QSERDES_COM_CLK_ENABLE1                                0x038
+#define QSERDES_COM_SYS_CLK_CTRL                       0x03c
+#define QSERDES_COM_SYSCLK_BUF_ENABLE                  0x040
+#define QSERDES_COM_PLL_IVCO                           0x048
+#define QSERDES_COM_LOCK_CMP1_MODE0                    0x04c
+#define QSERDES_COM_LOCK_CMP2_MODE0                    0x050
+#define QSERDES_COM_LOCK_CMP3_MODE0                    0x054
+#define QSERDES_COM_LOCK_CMP1_MODE1                    0x058
+#define QSERDES_COM_LOCK_CMP2_MODE1                    0x05c
+#define QSERDES_COM_LOCK_CMP3_MODE1                    0x060
+#define QSERDES_COM_BG_TRIM                            0x070
+#define QSERDES_COM_CLK_EP_DIV                         0x074
+#define QSERDES_COM_CP_CTRL_MODE0                      0x078
+#define QSERDES_COM_CP_CTRL_MODE1                      0x07c
+#define QSERDES_COM_PLL_RCTRL_MODE0                    0x084
+#define QSERDES_COM_PLL_RCTRL_MODE1                    0x088
+#define QSERDES_COM_PLL_CCTRL_MODE0                    0x090
+#define QSERDES_COM_PLL_CCTRL_MODE1                    0x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM                        0x0a8
+#define QSERDES_COM_SYSCLK_EN_SEL                      0x0ac
+#define QSERDES_COM_RESETSM_CNTRL                      0x0b4
+#define QSERDES_COM_RESETSM_CNTRL2                     0x0b8
+#define QSERDES_COM_RESTRIM_CTRL                       0x0bc
+#define QSERDES_COM_RESCODE_DIV_NUM                    0x0c4
+#define QSERDES_COM_LOCK_CMP_EN                                0x0c8
+#define QSERDES_COM_LOCK_CMP_CFG                       0x0cc
+#define QSERDES_COM_DEC_START_MODE0                    0x0d0
+#define QSERDES_COM_DEC_START_MODE1                    0x0d4
+#define QSERDES_COM_DIV_FRAC_START1_MODE0              0x0dc
+#define QSERDES_COM_DIV_FRAC_START2_MODE0              0x0e0
+#define QSERDES_COM_DIV_FRAC_START3_MODE0              0x0e4
+#define QSERDES_COM_DIV_FRAC_START1_MODE1              0x0e8
+#define QSERDES_COM_DIV_FRAC_START2_MODE1              0x0ec
+#define QSERDES_COM_DIV_FRAC_START3_MODE1              0x0f0
+#define QSERDES_COM_INTEGLOOP_INITVAL                  0x100
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0              0x108
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0              0x10c
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1              0x110
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1              0x114
+#define QSERDES_COM_VCO_TUNE_CTRL                      0x124
+#define QSERDES_COM_VCO_TUNE_MAP                       0x128
+#define QSERDES_COM_VCO_TUNE1_MODE0                    0x12c
+#define QSERDES_COM_VCO_TUNE2_MODE0                    0x130
+#define QSERDES_COM_VCO_TUNE1_MODE1                    0x134
+#define QSERDES_COM_VCO_TUNE2_MODE1                    0x138
+#define QSERDES_COM_VCO_TUNE_INITVAL1                  0x13c
+#define QSERDES_COM_VCO_TUNE_INITVAL2                  0x140
+#define QSERDES_COM_VCO_TUNE_TIMER1                    0x144
+#define QSERDES_COM_VCO_TUNE_TIMER2                    0x148
+#define QSERDES_COM_BG_CTRL                            0x170
+#define QSERDES_COM_CLK_SELECT                         0x174
+#define QSERDES_COM_HSCLK_SEL                          0x178
+#define QSERDES_COM_CORECLK_DIV                                0x184
+#define QSERDES_COM_CORE_CLK_EN                                0x18c
+#define QSERDES_COM_C_READY_STATUS                     0x190
+#define QSERDES_COM_CMN_CONFIG                         0x194
+#define QSERDES_COM_SVS_MODE_CLK_SEL                   0x19c
+#define QSERDES_COM_DEBUG_BUS0                         0x1a0
+#define QSERDES_COM_DEBUG_BUS1                         0x1a4
+#define QSERDES_COM_DEBUG_BUS2                         0x1a8
+#define QSERDES_COM_DEBUG_BUS3                         0x1ac
+#define QSERDES_COM_DEBUG_BUS_SEL                      0x1b0
+#define QSERDES_COM_CORECLK_DIV_MODE1                  0x1bc
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
new file mode 100644 (file)
index 0000000..583098a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_H_
+
+/* Only for QMP V2 PHY - TX registers */
+#define QSERDES_TX_EMP_POST1_LVL                       0x018
+#define QSERDES_TX_SLEW_CNTL                           0x040
+#define QSERDES_TX_RES_CODE_LANE_OFFSET                        0x054
+#define QSERDES_TX_DEBUG_BUS_SEL                       0x064
+#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN    0x068
+#define QSERDES_TX_LANE_MODE                           0x094
+#define QSERDES_TX_RCV_DETECT_LVL_2                    0x0ac
+
+/* Only for QMP V2 PHY - RX registers */
+#define QSERDES_RX_UCDR_SO_GAIN_HALF                   0x010
+#define QSERDES_RX_UCDR_SO_GAIN                                0x01c
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF               0x030
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER            0x034
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH             0x038
+#define QSERDES_RX_UCDR_SVS_SO_GAIN                    0x03c
+#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN               0x040
+#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE       0x048
+#define QSERDES_RX_RX_TERM_BW                          0x090
+#define QSERDES_RX_RX_EQ_GAIN1_LSB                     0x0c4
+#define QSERDES_RX_RX_EQ_GAIN1_MSB                     0x0c8
+#define QSERDES_RX_RX_EQ_GAIN2_LSB                     0x0cc
+#define QSERDES_RX_RX_EQ_GAIN2_MSB                     0x0d0
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2               0x0d8
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3               0x0dc
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4               0x0e0
+#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1         0x108
+#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2            0x10c
+#define QSERDES_RX_SIGDET_ENABLES                      0x110
+#define QSERDES_RX_SIGDET_CNTRL                                0x114
+#define QSERDES_RX_SIGDET_LVL                          0x118
+#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL               0x11c
+#define QSERDES_RX_RX_BAND                             0x120
+#define QSERDES_RX_RX_INTERFACE_MODE                   0x12c
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index b2aeace..6a24d61 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -6,6 +6,9 @@
 #ifndef QCOM_PHY_QMP_H_
 #define QCOM_PHY_QMP_H_
 
+#include "phy-qcom-qmp-qserdes-com.h"
+#include "phy-qcom-qmp-qserdes-txrx.h"
+
 /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
 
 #define QSERDES_PLL_BG_TIMER                           0x00c
@@ -64,115 +67,6 @@
 #define QSERDES_PLL_SVS_MODE_CLK_SEL                   0x194
 #define QSERDES_PLL_CORECLK_DIV_MODE1                  0x1b4
 
-/* Only for QMP V2 PHY - QSERDES COM registers */
-#define QSERDES_COM_BG_TIMER                           0x00c
-#define QSERDES_COM_SSC_EN_CENTER                      0x010
-#define QSERDES_COM_SSC_ADJ_PER1                       0x014
-#define QSERDES_COM_SSC_ADJ_PER2                       0x018
-#define QSERDES_COM_SSC_PER1                           0x01c
-#define QSERDES_COM_SSC_PER2                           0x020
-#define QSERDES_COM_SSC_STEP_SIZE1                     0x024
-#define QSERDES_COM_SSC_STEP_SIZE2                     0x028
-#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN                        0x034
-#define QSERDES_COM_CLK_ENABLE1                                0x038
-#define QSERDES_COM_SYS_CLK_CTRL                       0x03c
-#define QSERDES_COM_SYSCLK_BUF_ENABLE                  0x040
-#define QSERDES_COM_PLL_IVCO                           0x048
-#define QSERDES_COM_LOCK_CMP1_MODE0                    0x04c
-#define QSERDES_COM_LOCK_CMP2_MODE0                    0x050
-#define QSERDES_COM_LOCK_CMP3_MODE0                    0x054
-#define QSERDES_COM_LOCK_CMP1_MODE1                    0x058
-#define QSERDES_COM_LOCK_CMP2_MODE1                    0x05c
-#define QSERDES_COM_LOCK_CMP3_MODE1                    0x060
-#define QSERDES_COM_BG_TRIM                            0x070
-#define QSERDES_COM_CLK_EP_DIV                         0x074
-#define QSERDES_COM_CP_CTRL_MODE0                      0x078
-#define QSERDES_COM_CP_CTRL_MODE1                      0x07c
-#define QSERDES_COM_PLL_RCTRL_MODE0                    0x084
-#define QSERDES_COM_PLL_RCTRL_MODE1                    0x088
-#define QSERDES_COM_PLL_CCTRL_MODE0                    0x090
-#define QSERDES_COM_PLL_CCTRL_MODE1                    0x094
-#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM                        0x0a8
-#define QSERDES_COM_SYSCLK_EN_SEL                      0x0ac
-#define QSERDES_COM_RESETSM_CNTRL                      0x0b4
-#define QSERDES_COM_RESETSM_CNTRL2                     0x0b8
-#define QSERDES_COM_RESTRIM_CTRL                       0x0bc
-#define QSERDES_COM_RESCODE_DIV_NUM                    0x0c4
-#define QSERDES_COM_LOCK_CMP_EN                                0x0c8
-#define QSERDES_COM_LOCK_CMP_CFG                       0x0cc
-#define QSERDES_COM_DEC_START_MODE0                    0x0d0
-#define QSERDES_COM_DEC_START_MODE1                    0x0d4
-#define QSERDES_COM_DIV_FRAC_START1_MODE0              0x0dc
-#define QSERDES_COM_DIV_FRAC_START2_MODE0              0x0e0
-#define QSERDES_COM_DIV_FRAC_START3_MODE0              0x0e4
-#define QSERDES_COM_DIV_FRAC_START1_MODE1              0x0e8
-#define QSERDES_COM_DIV_FRAC_START2_MODE1              0x0ec
-#define QSERDES_COM_DIV_FRAC_START3_MODE1              0x0f0
-#define QSERDES_COM_INTEGLOOP_INITVAL                  0x100
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0              0x108
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0              0x10c
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1              0x110
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1              0x114
-#define QSERDES_COM_VCO_TUNE_CTRL                      0x124
-#define QSERDES_COM_VCO_TUNE_MAP                       0x128
-#define QSERDES_COM_VCO_TUNE1_MODE0                    0x12c
-#define QSERDES_COM_VCO_TUNE2_MODE0                    0x130
-#define QSERDES_COM_VCO_TUNE1_MODE1                    0x134
-#define QSERDES_COM_VCO_TUNE2_MODE1                    0x138
-#define QSERDES_COM_VCO_TUNE_INITVAL1                  0x13c
-#define QSERDES_COM_VCO_TUNE_INITVAL2                  0x140
-#define QSERDES_COM_VCO_TUNE_TIMER1                    0x144
-#define QSERDES_COM_VCO_TUNE_TIMER2                    0x148
-#define QSERDES_COM_BG_CTRL                            0x170
-#define QSERDES_COM_CLK_SELECT                         0x174
-#define QSERDES_COM_HSCLK_SEL                          0x178
-#define QSERDES_COM_CORECLK_DIV                                0x184
-#define QSERDES_COM_CORE_CLK_EN                                0x18c
-#define QSERDES_COM_C_READY_STATUS                     0x190
-#define QSERDES_COM_CMN_CONFIG                         0x194
-#define QSERDES_COM_SVS_MODE_CLK_SEL                   0x19c
-#define QSERDES_COM_DEBUG_BUS0                         0x1a0
-#define QSERDES_COM_DEBUG_BUS1                         0x1a4
-#define QSERDES_COM_DEBUG_BUS2                         0x1a8
-#define QSERDES_COM_DEBUG_BUS3                         0x1ac
-#define QSERDES_COM_DEBUG_BUS_SEL                      0x1b0
-#define QSERDES_COM_CORECLK_DIV_MODE1                  0x1bc
-
-/* Only for QMP V2 PHY - TX registers */
-#define QSERDES_TX_EMP_POST1_LVL                       0x018
-#define QSERDES_TX_SLEW_CNTL                           0x040
-#define QSERDES_TX_RES_CODE_LANE_OFFSET                        0x054
-#define QSERDES_TX_DEBUG_BUS_SEL                       0x064
-#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN    0x068
-#define QSERDES_TX_LANE_MODE                           0x094
-#define QSERDES_TX_RCV_DETECT_LVL_2                    0x0ac
-
-/* Only for QMP V2 PHY - RX registers */
-#define QSERDES_RX_UCDR_SO_GAIN_HALF                   0x010
-#define QSERDES_RX_UCDR_SO_GAIN                                0x01c
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF               0x030
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER            0x034
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH             0x038
-#define QSERDES_RX_UCDR_SVS_SO_GAIN                    0x03c
-#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN               0x040
-#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE       0x048
-#define QSERDES_RX_RX_TERM_BW                          0x090
-#define QSERDES_RX_RX_EQ_GAIN1_LSB                     0x0c4
-#define QSERDES_RX_RX_EQ_GAIN1_MSB                     0x0c8
-#define QSERDES_RX_RX_EQ_GAIN2_LSB                     0x0cc
-#define QSERDES_RX_RX_EQ_GAIN2_MSB                     0x0d0
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2               0x0d8
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3               0x0dc
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4               0x0e0
-#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1         0x108
-#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2            0x10c
-#define QSERDES_RX_SIGDET_ENABLES                      0x110
-#define QSERDES_RX_SIGDET_CNTRL                                0x114
-#define QSERDES_RX_SIGDET_LVL                          0x118
-#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL               0x11c
-#define QSERDES_RX_RX_BAND                             0x120
-#define QSERDES_RX_RX_INTERFACE_MODE                   0x12c
-
 /* Only for QMP V2 PHY - PCS registers */
 #define QPHY_V2_PCS_POWER_DOWN_CONTROL                         0x04
 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0                           0x24