spi: bcm2835: support effective_speed_hz

Setting spi_transfer->effective_speed_hz in transfer_one so that
it can get used in cs_change_delay configured with delay as a muliple
of SPI clock cycles.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20200709074120.110069-2-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index e9a91ad..c45d76c 100644 (file)
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -1082,7 +1082,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
                                    struct spi_transfer *tfr)
 {
        struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
-       unsigned long spi_hz, clk_hz, cdiv, spi_used_hz;
+       unsigned long spi_hz, clk_hz, cdiv;
        unsigned long hz_per_byte, byte_limit;
        u32 cs = bs->prepare_cs[spi->chip_select];
 
@@ -1102,7 +1102,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
        } else {
                cdiv = 0; /* 0 is the slowest we can go */
        }
-       spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
+       tfr->effective_speed_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
        bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
 
        /* handle all the 3-wire mode */
@@ -1122,7 +1122,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
         * per 300,000 Hz of bus clock.
         */
        hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
-       byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;
+       byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
 
        /* run in polling mode for short transfers */
        if (tfr->len < byte_limit)