drm/i915: Relocate FBC_LLC_READ_CTRL

In the case of FBC_LLC_READ_CTRL the "FBC" stands for
frame buffer _caching_, not frame buffer compression.
Move the register definition out from the middle of the
frame buffer compression register definitions. Let's
just stick it somewhere with similar looking register
offsets.

And while at it switch it over to REG_BIT().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211104144520.22605-15-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a8c294..7d182d2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -371,6 +371,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VLV_G3DCTL             _MMIO(0x9024)
 #define VLV_GSCKGCTL           _MMIO(0x9028)
 
+#define FBC_LLC_READ_CTRL      _MMIO(0x9044)
+#define   FBC_LLC_FULLY_OPEN   REG_BIT(30)
+
 #define GEN6_MBCTL             _MMIO(0x0907c)
 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
 #define   GEN6_MBCTL_CTX_FETCH_NEEDED  (1 << 3)
@@ -3348,9 +3351,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define FBC_LL_SIZE            (1536)
 
-#define FBC_LLC_READ_CTRL      _MMIO(0x9044)
-#define   FBC_LLC_FULLY_OPEN   (1 << 30)
-
 /* Framebuffer compression for GM45+ */
 #define DPFC_CB_BASE           _MMIO(0x3200)
 #define ILK_DPFC_CB_BASE       _MMIO(0x43200)