add %eax, %eax
-# ALL: Iterations: 100
-# ALL-NEXT: Instructions: 100
-# ALL-NEXT: Total Cycles: 103
-# ALL-NEXT: Dispatch Width: 2
-# ALL-NEXT: IPC: 0.97
-# ALL-NEXT: Block RThroughput: 0.5
+# FULLREPORT: Iterations: 100
+# FULLREPORT-NEXT: Instructions: 100
+# FULLREPORT-NEXT: Total Cycles: 103
+# FULLREPORT-NEXT: Dispatch Width: 2
+# FULLREPORT-NEXT: IPC: 0.97
+# FULLREPORT-NEXT: Block RThroughput: 0.5
# ALL: Instruction Info:
# ALL-NEXT: [1]: #uOps
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT
-# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=true < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT
-# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOREPORT
-# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=DEFAULTREPORT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views < %s | FileCheck %s -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=true < %s | FileCheck %s -check-prefix=DEFAULTREPORT -check-prefix=FULLREPORT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false < %s | FileCheck %s -check-prefix=NOREPORT -allow-empty
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=DEFAULTREPORT
add %eax, %eax
-# ALL: Iterations: 100
-# ALL-NEXT: Instructions: 100
-# ALL-NEXT: Total Cycles: 103
-# ALL-NEXT: Dispatch Width: 2
-# ALL-NEXT: IPC: 0.97
-# ALL-NEXT: Block RThroughput: 0.5
+# NOREPORT-NOT: {{.}}
+
+# DEFAULTREPORT: Iterations: 100
+# DEFAULTREPORT-NEXT: Instructions: 100
+# DEFAULTREPORT-NEXT: Total Cycles: 103
+# DEFAULTREPORT-NEXT: Dispatch Width: 2
+# DEFAULTREPORT-NEXT: IPC: 0.97
+# DEFAULTREPORT-NEXT: Block RThroughput: 0.5
# DEFAULTREPORT: Instruction Info:
# DEFAULTREPORT-NEXT: [1]: #uOps
xor %eax, %ebx
-# ALL: Iterations: 1
-# ALL-NEXT: Instructions: 1
-# ALL-NEXT: Total Cycles: 4
-
-# BDW-NEXT: Dispatch Width: 4
-# BTVER2-NEXT: Dispatch Width: 2
-# HSW-NEXT: Dispatch Width: 4
-# IVB-NEXT: Dispatch Width: 4
-# KNL-NEXT: Dispatch Width: 4
-# SKX-NEXT: Dispatch Width: 6
-# SKX-AVX512-NEXT: Dispatch Width: 6
-# SLM-NEXT: Dispatch Width: 2
-# SNB-NEXT: Dispatch Width: 4
-# ZNVER1-NEXT: Dispatch Width: 4
-
-# ALL-NEXT: IPC: 0.25
-
-# BDW-NEXT: Block RThroughput: 0.3
-# BTVER2-NEXT: Block RThroughput: 0.5
-# HSW-NEXT: Block RThroughput: 0.3
-# IVB-NEXT: Block RThroughput: 0.3
-# KNL-NEXT: Block RThroughput: 0.3
-# SKX-NEXT: Block RThroughput: 0.3
-# SKX-AVX512-NEXT: Block RThroughput: 0.3
-# SLM-NEXT: Block RThroughput: 0.5
-# SNB-NEXT: Block RThroughput: 0.3
-# ZNVER1-NEXT: Block RThroughput: 0.3
-
# ALL: Register File statistics:
# ALL-NEXT: Total number of mappings created: 2
# ALL-NEXT: Max number of mappings used: 2
xor %eax, %ebx
-# ALL: Iterations: 1
-# ALL-NEXT: Instructions: 1
-# ALL-NEXT: Total Cycles: 4
-
-# BDW-NEXT: Dispatch Width: 4
-# BTVER2-NEXT: Dispatch Width: 2
-# HSW-NEXT: Dispatch Width: 4
-# IVB-NEXT: Dispatch Width: 4
-# KNL-NEXT: Dispatch Width: 4
-# SKX-NEXT: Dispatch Width: 6
-# SKX-AVX512-NEXT: Dispatch Width: 6
-# SLM-NEXT: Dispatch Width: 2
-# SNB-NEXT: Dispatch Width: 4
-# ZNVER1-NEXT: Dispatch Width: 4
-
-# ALL-NEXT: IPC: 0.25
-
-# BDW-NEXT: Block RThroughput: 0.3
-# BTVER2-NEXT: Block RThroughput: 0.5
-# HSW-NEXT: Block RThroughput: 0.3
-# IVB-NEXT: Block RThroughput: 0.3
-# KNL-NEXT: Block RThroughput: 0.3
-# SKX-NEXT: Block RThroughput: 0.3
-# SKX-AVX512-NEXT: Block RThroughput: 0.3
-# SLM-NEXT: Block RThroughput: 0.5
-# SNB-NEXT: Block RThroughput: 0.3
-# ZNVER1-NEXT: Block RThroughput: 0.3
-
# ALL: Schedulers - number of cycles where we saw N instructions issued:
# ALL-NEXT: [# issued], [# cycles]
# ALL-NEXT: 0, 3 (75.0%)
cl::desc("Print dispatch statistics"),
cl::cat(ViewOptions), cl::init(false));
+static cl::opt<bool>
+ PrintSummaryView("summary-view", cl::Hidden,
+ cl::desc("Print summary view (enabled by default)"),
+ cl::cat(ViewOptions), cl::init(true));
+
static cl::opt<bool> PrintSchedulerStats("scheduler-stats",
cl::desc("Print scheduler statistics"),
cl::cat(ViewOptions), cl::init(false));
return;
if (EnableAllViews.getNumOccurrences()) {
+ processOptionImpl(PrintSummaryView, EnableAllViews);
processOptionImpl(PrintResourcePressureView, EnableAllViews);
processOptionImpl(PrintTimelineView, EnableAllViews);
processOptionImpl(PrintInstructionInfoView, EnableAllViews);
EnableAllViews.getPosition() < EnableAllStats.getPosition()
? EnableAllStats
: EnableAllViews;
+ processOptionImpl(PrintSummaryView, Default);
processOptionImpl(PrintRegisterFileStats, Default);
processOptionImpl(PrintDispatchStats, Default);
processOptionImpl(PrintSchedulerStats, Default);
LoadQueueSize, StoreQueueSize, AssumeNoAlias);
mca::BackendPrinter Printer(B);
- Printer.addView(llvm::make_unique<mca::SummaryView>(SM, S, Width));
+ if (PrintSummaryView)
+ Printer.addView(llvm::make_unique<mca::SummaryView>(SM, S, Width));
+
if (PrintInstructionInfoView)
Printer.addView(
llvm::make_unique<mca::InstructionInfoView>(*STI, *MCII, S, *IP));