Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"
authorHelge Deller <deller@gmx.de>
Sat, 7 May 2022 13:31:16 +0000 (15:31 +0200)
committerHelge Deller <deller@gmx.de>
Sun, 8 May 2022 18:01:11 +0000 (20:01 +0200)
This reverts commit afdb4a5b1d340e4afffc65daa21cc71890d7d589.

It triggers RCU stalls at boot with a 32-bit kernel.

Signed-off-by: Helge Deller <deller@gmx.de>
Noticed-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org # v5.16+
arch/parisc/kernel/time.c

index bb27dfeeddfcc2f776c70ccf0a84df3c8971da09..95ee9e1a364b57bfc95642ac554e77af7dd3b90d 100644 (file)
@@ -251,16 +251,30 @@ void __init time_init(void)
 static int __init init_cr16_clocksource(void)
 {
        /*
-        * The cr16 interval timers are not syncronized across CPUs, even if
-        * they share the same socket.
+        * The cr16 interval timers are not syncronized across CPUs on
+        * different sockets, so mark them unstable and lower rating on
+        * multi-socket SMP systems.
         */
        if (num_online_cpus() > 1 && !running_on_qemu) {
-               /* mark sched_clock unstable */
-               clear_sched_clock_stable();
-
-               clocksource_cr16.name = "cr16_unstable";
-               clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
-               clocksource_cr16.rating = 0;
+               int cpu;
+               unsigned long cpu0_loc;
+               cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
+
+               for_each_online_cpu(cpu) {
+                       if (cpu == 0)
+                               continue;
+                       if ((cpu0_loc != 0) &&
+                           (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc))
+                               continue;
+
+                       /* mark sched_clock unstable */
+                       clear_sched_clock_stable();
+
+                       clocksource_cr16.name = "cr16_unstable";
+                       clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
+                       clocksource_cr16.rating = 0;
+                       break;
+               }
        }
 
        /* register at clocksource framework */