Known = Known.intersectWith(Known2);
break;
}
+ case RISCVISD::CZERO_EQZ:
+ case RISCVISD::CZERO_NEZ:
+ Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
+ // Result is either all zero or operand 0. We can propagate zeros, but not
+ // ones.
+ Known.One.clearAllBits();
+ break;
case RISCVISD::REMUW: {
KnownBits Known2;
Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, a2
; RV32ZICOND-NEXT: or a0, a1, a0
-; RV32ZICOND-NEXT: li a1, 1
-; RV32ZICOND-NEXT: bne a0, a1, .LBB55_2
+; RV32ZICOND-NEXT: beqz a0, .LBB55_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
; RV32ZICOND-NEXT: li a0, 0
; RV32ZICOND-NEXT: ret
; RV32ZICOND-NEXT: sltu a0, a0, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, a4
; RV32ZICOND-NEXT: or a0, a1, a0
-; RV32ZICOND-NEXT: li a1, 1
-; RV32ZICOND-NEXT: bne a0, a1, .LBB59_2
+; RV32ZICOND-NEXT: beqz a0, .LBB59_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
; RV32ZICOND-NEXT: li a0, 0
; RV32ZICOND-NEXT: ret
; RV32ZICOND-NEXT: sltu a1, a2, a1
; RV32ZICOND-NEXT: czero.eqz a1, a1, a3
; RV32ZICOND-NEXT: or a0, a1, a0
-; RV32ZICOND-NEXT: li a1, 1
-; RV32ZICOND-NEXT: bne a0, a1, .LBB65_2
+; RV32ZICOND-NEXT: beqz a0, .LBB65_2
; RV32ZICOND-NEXT: # %bb.1: # %overflow
; RV32ZICOND-NEXT: li a0, 0
; RV32ZICOND-NEXT: ret