#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */
+
#define IS_830(dev) (dev == 0x3577)
#define IS_845(dev) (dev == 0x2562)
#define IS_85X(dev) (dev == 0x3582)
#define IS_I965GM(dev) (dev == 0x2A02)
+#define IS_VALLEYVIEW(dev) (dev == 0xf30)
+
#define IS_GEN4(dev) (dev == 0x2972 || \
dev == 0x2982 || \
dev == 0x2992 || \
dev == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid))
+ IS_HASWELL(devid) || \
+ IS_VALLEYVIEW(devid))
#define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_GT2 || \