}
/* Addresses computation */
-static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
+static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
{
- tcg_gen_add_tl(t0, t0, t1);
+ tcg_gen_add_tl(ret, arg0, arg1);
#if defined(TARGET_MIPS64)
/* For compatibility with 32-bit code, data reference in user mode
See the MIPS64 PRA manual, section 4.10. */
if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(ctx->hflags & MIPS_HFLAG_UX)) {
- tcg_gen_ext32s_i64(t0, t0);
+ tcg_gen_ext32s_i64(ret, ret);
}
#endif
}
gen_load_gpr(t0, base);
} else {
tcg_gen_movi_tl(t0, offset);
- gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
gen_load_gpr(t0, base);
} else {
tcg_gen_movi_tl(t0, offset);
- gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
gen_load_gpr(t0, base);
} else {
tcg_gen_movi_tl(t0, offset);
- gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
gen_load_gpr(t0, base);
} else {
gen_load_gpr(t0, index);
- gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+ gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */