arm64: dts: imx8mp: Add MEDIAMIX power domains
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Wed, 6 Apr 2022 15:34:00 +0000 (17:34 +0200)
committerShawn Guo <shawnguo@kernel.org>
Thu, 5 May 2022 01:32:55 +0000 (09:32 +0800)
Add the power domains related to the MEDIAMIX to the GPC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8mp.dtsi

index 3a59ce2..a0b4957 100644 (file)
                                        #address-cells = <1>;
                                        #size-cells = <0>;
 
+                                       pgc_mipi_phy1: power-domain@0 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+                                       };
+
                                        pgc_pcie_phy: power-domain@1 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
                                                power-domains = <&pgc_gpumix>;
                                        };
 
+                                       pgc_mediamix: power-domain@10 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+                                               clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+                                       };
+
+                                       pgc_mipi_phy2: power-domain@16 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+                                       };
+
                                        pgc_hsiomix: power-domains@17 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
                                                assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
                                                assigned-clock-rates = <500000000>;
                                        };
+
+                                       pgc_ispdwp: power-domain@18 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+                                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+                                       };
                                };
                        };
                };