+2022-04-05 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/extend.texi (Common Function Attributes): Document that
+ 'access' does not imply 'nonnull'.
+
+2022-04-05 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105139
+ * config/i386/mmx.md (*movv2qi_internal):
+ Change insn mode of alternative 5 to HF for TARGET_AVX512FP16.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.md (aarch64_cpymemdi): Turn into a
+ define_expand and turn operands 0 and 1 from REGs to MEMs.
+ (*aarch64_cpymemdi): New pattern.
+ (aarch64_setmemdi): Turn into a define_expand and turn operand 0
+ from a REG to a MEM.
+ (*aarch64_setmemdi): New pattern.
+ * config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Use
+ copy_to_mode_reg on all three registers. Replace the original
+ MEM addresses rather than creating wild reads and writes.
+ (aarch64_expand_setmem_mops): Likewise for the size and for the
+ destination memory and address.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/103147
+ * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): New class.
+ * config/aarch64/aarch64-sve-builtins.h (sve_switcher): Inherit
+ from aarch64_simd_switcher.
+ * config/aarch64/aarch64-builtins.cc (aarch64_simd_tuple_modes):
+ New variable.
+ (aarch64_lookup_simd_builtin_type): Use it instead of TYPE_MODE.
+ (register_tuple_type): Add more asserts. Expect the alignment
+ of the structure to be subject to flag_pack_struct and
+ maximum_field_alignment. Set aarch64_simd_tuple_modes.
+ (aarch64_simd_switcher::aarch64_simd_switcher): New function.
+ (aarch64_simd_switcher::~aarch64_simd_switcher): Likewise.
+ (handle_arm_neon_h): Hold an aarch64_simd_switcher throughout.
+ (aarch64_general_init_builtins): Hold an aarch64_simd_switcher
+ while calling aarch64_init_simd_builtins.
+ * config/aarch64/aarch64-sve-builtins.cc (sve_switcher::sve_switcher)
+ (sve_switcher::~sve_switcher): Remove code now performed by
+ aarch64_simd_switcher.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/104897
+ * config/aarch64/aarch64-sve-builtins.cc
+ (function_resolver::infer_vector_or_tuple_type): Use error_n
+ for "%d vectors" messages.
+
+2022-04-05 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * omp-low.cc (lower_omp_target): Use outer context looked-up 'var' as
+ argument to lang_hooks.decls.omp_array_data, instead of 'ovar' from
+ current clause.
+
+2022-04-05 Richard Biener <rguenther@suse.de>
+
+ PR c/105151
+ * passes.def (pass_walloca): Move early instance into
+ pass_build_ssa_passes to make SSA form available.
+
+2022-04-05 liuhongt <hongtao.liu@intel.com>
+
+ PR target/101908
+ * config/i386/i386.cc (ix86_split_stlf_stall_load): New
+ function
+ (ix86_reorg): Call ix86_split_stlf_stall_load.
+ * config/i386/i386.opt (-param=x86-stlf-window-ninsns=): New
+ param.
+
+2022-04-05 Alexandre Oliva <oliva@adacore.com>
+
+ * targhooks.cc (default_zero_call_used_regs): Attempt to group
+ regs that the target refuses to use in their natural modes.
+ (zcur_select_mode_rtx): New.
+ * regs.h (struct target_regs): Add x_hard_regno_max_nregs.
+ (hard_regno_max_nregs): Define.
+ * reginfo.cc (init_reg_modes_target): Set hard_regno_max_nregs.
+
2022-04-04 Alex Coplan <alex.coplan@arm.com>
* doc/match-and-simplify.texi: Fix typos.
+2022-04-05 Jason Merrill <jason@redhat.com>
+
+ PR c++/103852
+ DR 1286
+ * pt.cc (do_class_deduction): Pedwarn for renaming alias in C++17.
+
+2022-04-05 Jason Merrill <jason@redhat.com>
+
+ PR c++/101677
+ * name-lookup.h (struct cp_binding_level): Add requires_expression
+ bit-field.
+ * parser.cc (cp_parser_requires_expression): Set it.
+ (synthesize_implicit_template_parm): Check it.
+
2022-04-04 Jason Merrill <jason@redhat.com>
PR c++/101894
+2022-04-05 Sandra Loosemore <sandra@codesourcery.com>
+
+ * trans-openmp.cc (gfc_split_omp_clauses): Fix mask for
+ EXEC_OMP_MASKED_TASKLOOP.
+
+2022-04-05 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/104210
+ * arith.cc (eval_intrinsic): Avoid NULL pointer dereference.
+ (gfc_zero_size_array): Likewise.
+
+2022-04-05 Harald Anlauf <anlauf@gmx.de>
+ Steven G. Kargl <kargl@gcc.gnu.org>
+
+ PR fortran/105138
+ * intrinsic.cc (gfc_is_intrinsic): When a symbol refers to a
+ RECURSIVE procedure, it cannot be an INTRINSIC.
+
2022-03-30 Harald Anlauf <anlauf@gmx.de>
PR fortran/100892
+2022-04-05 Joseph Myers <joseph@codesourcery.com>
+
+ * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
+ ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
+ zh_TW.po: Update.
+
2022-04-04 Joseph Myers <joseph@codesourcery.com>
* sv.po: Update.
+2022-04-05 Sandra Loosemore <sandra@codesourcery.com>
+
+ * gfortran.dg/gomp/masked-taskloop.f90: New.
+
+2022-04-05 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105139
+ * gcc.target/i386/pr105139.c: New test.
+
+2022-04-05 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/104210
+ * gfortran.dg/pr104210.f90: New test.
+
+2022-04-05 Harald Anlauf <anlauf@gmx.de>
+ Steven G. Kargl <kargl@gcc.gnu.org>
+
+ PR fortran/105138
+ * gfortran.dg/recursive_reference_3.f90: New test.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gcc.target/aarch64/mops_4.c: New test.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/103147
+ * gcc.target/aarch64/pr103147-1.c: New test.
+ * gcc.target/aarch64/pr103147-2.c: Likewise.
+ * gcc.target/aarch64/pr103147-3.c: Likewise.
+ * gcc.target/aarch64/pr103147-4.c: Likewise.
+ * gcc.target/aarch64/pr103147-5.c: Likewise.
+ * gcc.target/aarch64/pr103147-6.c: Likewise.
+ * gcc.target/aarch64/pr103147-7.c: Likewise.
+ * gcc.target/aarch64/pr103147-8.c: Likewise.
+ * gcc.target/aarch64/pr103147-9.c: Likewise.
+ * gcc.target/aarch64/pr103147-10.c: Likewise.
+ * g++.target/aarch64/pr103147-1.C: Likewise.
+ * g++.target/aarch64/pr103147-2.C: Likewise.
+ * g++.target/aarch64/pr103147-3.C: Likewise.
+ * g++.target/aarch64/pr103147-4.C: Likewise.
+ * g++.target/aarch64/pr103147-5.C: Likewise.
+ * g++.target/aarch64/pr103147-6.C: Likewise.
+ * g++.target/aarch64/pr103147-7.C: Likewise.
+ * g++.target/aarch64/pr103147-8.C: Likewise.
+ * g++.target/aarch64/pr103147-9.C: Likewise.
+ * g++.target/aarch64/pr103147-10.C: Likewise.
+
+2022-04-05 Jason Merrill <jason@redhat.com>
+
+ PR c++/103852
+ DR 1286
+ * g++.dg/cpp1z/class-deduction-alias1.C: Expect warning.
+
+2022-04-05 Jason Merrill <jason@redhat.com>
+
+ PR c++/101677
+ * g++.dg/cpp2a/concepts-pr67178.C: Adjust error.
+ * g++.dg/cpp2a/concepts-requires28.C: New test.
+
+2022-04-05 Jason Merrill <jason@redhat.com>
+
+ * g++.dg/cpp0x/noexcept34.C: Allow more wording variation.
+
+2022-04-05 Richard Biener <rguenther@suse.de>
+
+ PR c/105151
+ * gcc.dg/gimplefe-error-14.c: New testcase.
+
+2022-04-05 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/zvector/vec-double-compile.c: Expect vl
+ instead of vc*.
+ * gcc.target/s390/zvector/vec-float-compile.c: Dito.
+ * gcc.target/s390/zvector/vec-signed-compile.c: Dito.
+ * gcc.target/s390/zvector/vec-unsigned-compile.c: Dito.
+
+2022-04-05 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/ifcvt-two-insns-bool.c: Change nle to h.
+ * gcc.target/s390/ifcvt-two-insns-int.c: Dito.
+ * gcc.target/s390/ifcvt-two-insns-long.c: Dito.
+
+2022-04-05 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.dg/Wuse-after-free-2.c:
+ Add -fno-tree-loop-distribute-patterns in order to avoid
+ rawmemchr.
+
+2022-04-05 liuhongt <hongtao.liu@intel.com>
+
+ * gcc.target/i386/pr101908-1.c: New test.
+ * gcc.target/i386/pr101908-2.c: New test.
+ * gcc.target/i386/pr101908-3.c: New test.
+
2022-04-04 Jason Merrill <jason@redhat.com>
PR c++/101894
+2022-04-05 Ian Lance Taylor <iant@golang.org>
+
+ * elf.c (elf_zlib_inflate): Don't skip initial aligned byte in
+ uncompressed block.
+
2022-02-17 Ian Lance Taylor <iant@golang.org>
* dwarf.c (find_address_ranges): Handle skeleton units.
+2022-04-05 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * testsuite/libgomp.fortran/use_device_ptr-4.f90: New testcase.
+
2022-04-04 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.fortran/examples-4/declare_target-1.f90: Use
projects / platform / upstream / gcc.git / commitdiff