b->shader->did_writeout = true;
b->shader->out->reads_tib = true;
- unsigned nr_comps = nir_dest_num_components(instr->dest);
+ unsigned nr_comps = instr->dest.ssa.num_components;
agx_ld_tile_to(b, dest, agx_src_index(&instr->src[0]),
agx_format_for_pipe(nir_intrinsic_format(instr)),
BITFIELD_MASK(nr_comps), nir_intrinsic_base(instr));
offset = agx_abs(offset);
agx_device_load_to(b, dest, addr, offset, fmt,
- BITFIELD_MASK(nir_dest_num_components(instr->dest)),
- shift, 0);
- agx_emit_cached_split(b, dest, nir_dest_num_components(instr->dest));
+ BITFIELD_MASK(instr->dest.ssa.num_components), shift, 0);
+ agx_emit_cached_split(b, dest, instr->dest.ssa.num_components);
}
static void
nir_intrinsic_instr *instr)
{
agx_index srcs[4] = {agx_null()};
- unsigned dim = nir_dest_num_components(instr->dest);
+ unsigned dim = instr->dest.ssa.num_components;
assert(dim <= ARRAY_SIZE(srcs) && "shouldn't see larger vectors");
unsigned base = nir_intrinsic_base(instr);
agx_load_compute_dimension(agx_builder *b, agx_index dst,
nir_intrinsic_instr *instr, enum agx_sr base)
{
- unsigned dim = nir_dest_num_components(instr->dest);
+ unsigned dim = instr->dest.ssa.num_components;
unsigned size = instr->dest.ssa.bit_size;
assert(size == 16 || size == 32);
assert(base.size == AGX_SIZE_16);
enum agx_format format = format_for_bitsize(instr->dest.ssa.bit_size);
- unsigned nr = nir_dest_num_components(instr->dest);
+ unsigned nr = instr->dest.ssa.num_components;
unsigned mask = BITFIELD_MASK(nr);
agx_local_load_to(b, dst, base, index, format, mask);
unsigned srcs = nir_op_infos[instr->op].num_inputs;
unsigned sz = instr->dest.dest.ssa.bit_size;
unsigned src_sz = srcs ? nir_src_bit_size(instr->src[0].src) : 0;
- ASSERTED unsigned comps = nir_dest_num_components(instr->dest.dest);
+ ASSERTED unsigned comps = instr->dest.dest.ssa.num_components;
assert(comps == 1 || nir_op_is_vec(instr->op));
assert(sz == 1 ||
nir_def *repl = NULL;
bool has_dest = (intr->intrinsic != nir_intrinsic_store_global);
- unsigned num_components = has_dest ? nir_dest_num_components(intr->dest) : 0;
+ unsigned num_components = has_dest ? intr->dest.ssa.num_components : 0;
unsigned bit_size = has_dest ? intr->dest.ssa.bit_size : 0;
if (intr->intrinsic == nir_intrinsic_load_global) {
/* Each component is loaded separated */
nir_def *values[NIR_MAX_VEC_COMPONENTS] = {NULL};
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
values[i] = interpolate_channel(b, intr, i);
}
- return nir_vec(b, values, nir_dest_num_components(intr->dest));
+ return nir_vec(b, values, intr->dest.ssa.num_components);
}
bool
height = depth;
/* How we finish depends on the size of the result */
- unsigned nr_comps = nir_dest_num_components(tex->dest);
+ unsigned nr_comps = tex->dest.ssa.num_components;
assert(nr_comps <= 3);
/* Adjust for LOD, do not adjust array size */
case nir_intrinsic_image_size:
case nir_intrinsic_bindless_image_size:
- nir_def_rewrite_uses(
- &intr->dest.ssa,
- txs_for_image(b, intr, nir_dest_num_components(intr->dest),
- intr->dest.ssa.bit_size));
+ nir_def_rewrite_uses(&intr->dest.ssa,
+ txs_for_image(b, intr, intr->dest.ssa.num_components,
+ intr->dest.ssa.bit_size));
return true;
case nir_intrinsic_image_texel_address:
if (nir_op_infos[instr->op].input_sizes[src] > 0)
return channel < nir_op_infos[instr->op].input_sizes[src];
- return channel < nir_dest_num_components(instr->dest.dest);
+ return channel < instr->dest.dest.ssa.num_components;
}
nir_component_mask_t
if (nir_op_infos[instr->op].input_sizes[src] > 0)
return nir_op_infos[instr->op].input_sizes[src];
- return nir_dest_num_components(instr->dest.dest);
+ return instr->dest.dest.ssa.num_components;
}
#define CASE_ALL_SIZES(op) \
return src.ssa->divergent;
}
-static inline unsigned
-nir_dest_num_components(nir_dest dest)
-{
- return dest.ssa.num_components;
-}
-
static inline bool
nir_dest_is_divergent(nir_dest dest)
{
return false;
/* We can't do expansions without a move in the middle */
- unsigned nr_components = nir_dest_num_components(generate_alu->dest.dest);
+ unsigned nr_components = generate_alu->dest.dest.ssa.num_components;
if (fsat->dest.dest.ssa.num_components != nr_components)
return false;
return false;
const uint8_t *const swizzle = instr->src[src].swizzle;
- const unsigned num_components = nir_dest_num_components(instr->dest.dest);
+ const unsigned num_components = instr->dest.dest.ssa.num_components;
if (instr->dest.dest.ssa.bit_size == 32) {
const float first = val[swizzle[0]].f32;
const uint8_t *const swizzle0 = instr->src[0].swizzle;
const uint8_t *const swizzle1 = instr->src[1].swizzle;
- const unsigned num_components = nir_dest_num_components(instr->dest.dest);
+ const unsigned num_components = instr->dest.dest.ssa.num_components;
if (instr->dest.dest.ssa.bit_size == 32) {
for (unsigned i = 0; i < num_components; i++) {
*/
if (has_dest) {
nir_push_else(b, NULL);
- undef = nir_undef(b, nir_dest_num_components(intr->dest),
+ undef = nir_undef(b, intr->dest.ssa.num_components,
intr->dest.ssa.bit_size);
}
}
return intrin->dest.ssa.bit_size == 64 &&
- nir_dest_num_components(intrin->dest) >= 3;
+ intrin->dest.ssa.num_components >= 3;
}
/**
nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr);
nir_alu_src *alu_src = exec_node_data(nir_alu_src, use_src, src);
- unsigned count = nir_dest_num_components(alu->dest.dest);
+ unsigned count = alu->dest.dest.ssa.num_components;
for (unsigned idx = 0; idx < count; ++idx)
alu_src->swizzle[idx] = swiz_map[alu_src->swizzle[idx]];
} else if (use_src->parent_instr->type == nir_instr_type_intrinsic) {
txd->src[tex->num_srcs + 1] = nir_tex_src_for_ssa(nir_tex_src_ddy, dfdy);
nir_def_init(&txd->instr, &txd->dest.ssa,
- nir_dest_num_components(tex->dest),
+ tex->dest.ssa.num_components,
tex->dest.ssa.bit_size);
nir_builder_instr_insert(b, &txd->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txd->dest.ssa);
txl->src[tex->num_srcs - 1] = nir_tex_src_for_ssa(nir_tex_src_lod, lod);
nir_def_init(&txl->instr, &txl->dest.ssa,
- nir_dest_num_components(tex->dest),
+ tex->dest.ssa.num_components,
tex->dest.ssa.bit_size);
nir_builder_instr_insert(b, &txl->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txl->dest.ssa);
assert(start_idx < nir_op_infos[vec->op].num_inputs);
nir_def *src = vec->src[start_idx].src.ssa;
- unsigned num_components = nir_dest_num_components(vec->dest.dest);
+ unsigned num_components = vec->dest.dest.ssa.num_components;
assert(num_components == nir_op_infos[vec->op].num_inputs);
unsigned write_mask = 0;
unsigned swiz[NIR_MAX_VEC_COMPONENTS] = { 0 };
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
swizzles[j][i] = src_alu->src[j].swizzle[i];
- unsigned dest_components = nir_dest_num_components(vec->dest.dest);
+ unsigned dest_components = vec->dest.dest.ssa.num_components;
assert(dest_components == nir_op_infos[vec->op].num_inputs);
/* Generate the final write mask */
if (vec->op == nir_op_mov || !nir_op_is_vec(vec->op))
return false;
- unsigned num_components = nir_dest_num_components(vec->dest.dest);
+ unsigned num_components = vec->dest.dest.ssa.num_components;
/* Special case: if all sources are the same, just swizzle instead to avoid
* the extra copies from a register.
->src);
nir_def_init(&phi->instr, &phi->dest.ssa,
- nir_dest_num_components(bcsel->dest.dest),
+ bcsel->dest.dest.ssa.num_components,
bcsel->dest.dest.ssa.bit_size);
b->cursor = nir_after_phis(header_block);
/* The conversion we are stripping off could have had a swizzle,
* so replace it with a mov if necessary:
*/
- unsigned num_comp = nir_dest_num_components(alu->dest.dest);
+ unsigned num_comp = alu->dest.dest.ssa.num_components;
new_src = nir_mov_alu(b, alu->src[0], num_comp);
}
default:
return false;
}
- unsigned num_components = nir_dest_num_components(alu->dest.dest);
+ unsigned num_components = alu->dest.dest.ssa.num_components;
b->cursor = nir_before_instr(&alu->instr);
nir_def *def = nir_undef(b, num_components, 32);
nir_def_rewrite_uses_after(&alu->dest.dest.ssa, def, &alu->instr);
*/
if (nir_intrinsic_infos[op].has_dest &&
nir_intrinsic_infos[op].dest_components == 0) {
- intrin->num_components = nir_dest_num_components(intrin->dest);
+ intrin->num_components = intrin->dest.ssa.num_components;
} else {
for (unsigned i = 0; i < num_srcs; i++) {
if (nir_intrinsic_infos[op].src_components[i] == 0) {
nir_variable *var = nir_intrinsic_get_var(intr, 0);
if (var->data.mode != nir_var_function_temp)
return false;
- return nir_dest_num_components(intr->dest) >= 3;
+ return intr->dest.ssa.num_components >= 3;
}
case nir_intrinsic_store_deref: {
if (nir_src_bit_size(intr->src[1]) != 64)
nir_phi_instr *phi = nir_instr_as_phi(instr);
if (phi->dest.ssa.bit_size != 64)
return false;
- return nir_dest_num_components(phi->dest) >= 3;
+ return phi->dest.ssa.num_components >= 3;
}
default:
* as the destination.
*/
validate_src(&instr->parent, state, instr->dest.ssa.bit_size,
- nir_dest_num_components(instr->dest));
+ instr->dest.ssa.num_components);
nir_instr *parent_instr = instr->parent.ssa->parent_instr;
case nir_intrinsic_load_reg:
case nir_intrinsic_load_reg_indirect:
validate_register_handle(instr->src[0],
- nir_dest_num_components(instr->dest),
+ instr->dest.ssa.num_components,
instr->dest.ssa.bit_size, state);
break;
}
/* General case: We can just grab the one used channel per src. */
- assert(nir_dest_num_components(alu->dest.dest) == 1);
+ assert(alu->dest.dest.ssa.num_components == 1);
for (int i = 0; i < info->num_inputs; i++) {
nir_alu_src *asrc = &alu->src[i];
type_t type;
opc_t opc = 0;
- ncomp = nir_dest_num_components(tex->dest);
+ ncomp = tex->dest.ssa.num_components;
coord = off = ddx = ddy = NULL;
lod = proj = compare = sample_index = NULL;
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMValueRef src[NIR_MAX_VEC_COMPONENTS];
unsigned src_bit_size[NIR_MAX_VEC_COMPONENTS];
- const unsigned num_components = nir_dest_num_components(instr->dest.dest);
+ const unsigned num_components = instr->dest.dest.ssa.num_components;
unsigned src_components;
switch (instr->op) {
var.data.driver_location = nir_intrinsic_base(instr);
var.data.location_frac = nir_intrinsic_component(instr);
- unsigned nc = nir_dest_num_components(instr->dest);
+ unsigned nc = instr->dest.ssa.num_components;
unsigned bit_size = instr->dest.ssa.bit_size;
nir_src offset = *nir_get_io_offset_src(instr);
LLVMValueRef val = bld_base->load_reg(bld_base, reg_bld, decl, base, indir_src, reg_storage);
- if (!is_aos(bld_base) && nir_dest_num_components(instr->dest) > 1) {
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); i++)
+ if (!is_aos(bld_base) && instr->dest.ssa.num_components > 1) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
result[i] = LLVMBuildExtractValue(builder, val, i, "");
} else {
result[0] = val;
LLVMValueRef indir_index;
LLVMValueRef indir_vertex_index = NULL;
unsigned vertex_index = 0;
- unsigned nc = nir_dest_num_components(instr->dest);
+ unsigned nc = instr->dest.ssa.num_components;
unsigned bit_size = instr->dest.ssa.bit_size;
if (var) {
bool vs_in = bld_base->shader->info.stage == MESA_SHADER_VERTEX &&
if (nir_src_num_components(instr->src[0]) == 1)
idx = LLVMBuildExtractElement(builder, idx, lp_build_const_int32(gallivm, 0), "");
- bld_base->load_ubo(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_ubo(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
offset_is_uniform, idx, offset, result);
}
LLVMValueRef idx = lp_build_const_int32(gallivm, 0);
bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
- bld_base->load_ubo(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_ubo(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
offset_is_uniform, idx, offset, result);
}
bool index_and_offset_are_uniform =
nir_src_is_always_uniform(instr->src[0]) &&
nir_src_is_always_uniform(instr->src[1]);
- bld_base->load_mem(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_mem(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
index_and_offset_are_uniform, false, idx, offset, result);
}
{
LLVMValueRef offset = get_src(bld_base, instr->src[0]);
bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
- bld_base->load_mem(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_mem(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
offset_is_uniform, false, NULL, offset, result);
}
LLVMValueRef offset = get_src(bld_base, instr->src[0]);
bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
- bld_base->load_kernel_arg(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_kernel_arg(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
nir_src_bit_size(instr->src[0]),
offset_is_uniform, offset, result);
{
LLVMValueRef addr = get_src(bld_base, instr->src[0]);
bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
- bld_base->load_global(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_global(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
nir_src_bit_size(instr->src[0]),
offset_is_uniform, addr, result);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
- unsigned num_components = nir_dest_num_components(instr->dest);
+ unsigned num_components = instr->dest.ssa.num_components;
nir_variable *var = nir_deref_instr_get_variable(deref);
unsigned const_index;
LLVMValueRef indir_index;
{
LLVMValueRef offset = get_src(bld_base, instr->src[0]);
- bld_base->load_scratch(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_scratch(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size, offset, result);
}
{
LLVMValueRef offset = get_src(bld_base, instr->src[0]);
bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
- bld_base->load_mem(bld_base, nir_dest_num_components(instr->dest),
+ bld_base->load_mem(bld_base, instr->dest.ssa.num_components,
instr->dest.ssa.bit_size,
offset_is_uniform, true, NULL, offset, result);
}
default:
unreachable("unexpected alu type");
}
- for (int i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (int i = 0; i < instr->dest.ssa.num_components; ++i) {
if (is_float) {
texel[i] = lp_build_float_to_half(gallivm, texel[i]);
} else {
!(src.src.is_ssa && src.src.ssa->parent_instr->type == nir_instr_type_ssa_undef)) {
int chan1 = 1;
if (nir_op_infos[instr->op].input_sizes[i] == 0) {
- chan1 = nir_dest_num_components(instr->dest.dest) > 1 ? 1 : 0;
+ chan1 = instr->dest.dest.ssa.num_components > 1 ? 1 : 0;
}
usrc = ureg_swizzle(usrc,
src.swizzle[0] * 2,
* aren't defined, even if they aren't really read. (GLSL compile fails on
* gl_NumWorkGroups.w, for example).
*/
- uint32_t write_mask = BITSET_MASK(nir_dest_num_components(instr->dest));
+ uint32_t write_mask = BITSET_MASK(instr->dest.ssa.num_components);
sv = ntt_swizzle_for_write_mask(sv, write_mask);
/* TGSI and NIR define these intrinsics as always loading ints, but they can
return false;
assert(intr->dest.ssa.bit_size >= 16 && "no 8-bit sysvals");
- unsigned dim = nir_dest_num_components(intr->dest);
+ unsigned dim = intr->dest.ssa.num_components;
unsigned element_size = intr->dest.ssa.bit_size / 16;
unsigned length = dim * element_size;
static bool
vec_dest_has_swizzle(nir_alu_instr *vec, nir_def *ssa)
{
- for (unsigned i = 0; i < nir_dest_num_components(vec->dest.dest); i++) {
+ for (unsigned i = 0; i < vec->dest.dest.ssa.num_components; i++) {
if (vec->src[i].src.ssa != ssa)
continue;
unsigned num_components = 1;
- for (unsigned i = start_idx + 1; i < nir_dest_num_components(vec->dest.dest); i++) {
+ for (unsigned i = start_idx + 1; i < vec->dest.dest.ssa.num_components; i++) {
if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src) &&
is_src_mod_neg(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx) &&
is_src_mod_abs(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx)) {
}
unsigned finished_write_mask = 0;
- for (unsigned i = 0; i < nir_dest_num_components(alu->dest.dest); i++) {
+ for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) {
nir_def *ssa = alu->src[i].src.ssa;
/* check that vecN instruction is only user of this */
if (intrin->intrinsic != nir_intrinsic_load_input)
return NULL;
- if (nir_dest_num_components(intrin->dest) != 4)
+ if (intrin->dest.ssa.num_components != 4)
return NULL;
/* Coords must be in .xyz */
uint8_t swizzle = alu->src[0].swizzle[0];
int i;
- for (i = 1; i < nir_dest_num_components(alu->dest.dest); i++)
+ for (i = 1; i < alu->dest.dest.ssa.num_components; i++)
if (alu->src[0].swizzle[i] != (swizzle + i))
break;
- if (i != nir_dest_num_components(alu->dest.dest))
+ if (i != alu->dest.dest.ssa.num_components)
return false;
/* mali4xx can't access unaligned vec3, don't split load input */
- if (nir_dest_num_components(alu->dest.dest) == 3 && swizzle > 0)
+ if (alu->dest.dest.ssa.num_components == 3 && swizzle > 0)
return false;
/* mali4xx can't access unaligned vec2, don't split load input */
- if (nir_dest_num_components(alu->dest.dest) == 2 &&
+ if (alu->dest.dest.ssa.num_components == 2 &&
swizzle != 0 && swizzle != 2)
return false;
b->shader,
intrin->intrinsic);
nir_def_init(&new_intrin->instr, &new_intrin->dest.ssa,
- nir_dest_num_components(alu->dest.dest), ssa->bit_size);
- new_intrin->num_components = nir_dest_num_components(alu->dest.dest);
+ alu->dest.dest.ssa.num_components, ssa->bit_size);
+ new_intrin->num_components = alu->dest.dest.ssa.num_components;
nir_intrinsic_set_base(new_intrin, nir_intrinsic_base(intrin));
nir_intrinsic_set_component(new_intrin, nir_intrinsic_component(intrin) + swizzle);
nir_intrinsic_set_dest_type(new_intrin, nir_intrinsic_dest_type(intrin));
return false;
}
- int num_components = nir_dest_num_components(alu->dest.dest);
+ int num_components = alu->dest.dest.ssa.num_components;
uint8_t swizzle = alu->src[0].swizzle[0];
static Pin
pin_for_components(const nir_alu_instr& alu)
{
- return nir_dest_num_components(alu.dest.dest) == 1 ? pin_free : pin_none;
+ return alu.dest.dest.ssa.num_components == 1 ? pin_free : pin_none;
}
static bool
swz[1] = 0;
}
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_chan),
value_factory.src64(alu.src[0], i, swz[0]),
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_free),
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_chan),
{
auto& value_factory = shader.value_factory();
- assert(nir_dest_num_components(alu.dest.dest) == 1);
+ assert(alu.dest.dest.ssa.num_components == 1);
shader.emit_instruction(new AluInstr(op1_mov,
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
{
auto& value_factory = shader.value_factory();
- assert(nir_dest_num_components(alu.dest.dest) == 1);
+ assert(alu.dest.dest.ssa.num_components == 1);
if (try_propagat_fsat64(alu, shader)) {
auto ir = new AluInstr(op1_mov,
int num_emit0 = opcode == op2_mul_64 ? 3 : 1;
- assert(num_emit0 == 1 || nir_dest_num_components(alu.dest.dest) == 1);
+ assert(num_emit0 == 1 || alu.dest.dest.ssa.num_components == 1);
- for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
+ for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
int i = 0;
for (; i < num_emit0; ++i) {
auto dest = i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan)
AluInstr::SrcValues src(4);
- for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
+ for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
auto dest = value_factory.dest(alu.dest.dest.ssa, 2 * k, pin_chan);
src[0] = value_factory.src64(alu.src[order[0]], k, 1);
src[1] = value_factory.src64(alu.src[order[1]], k, 1);
auto group = new AluGroup();
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(op2_and_int,
value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_group),
value_factory.src(alu.src[0], i),
auto group = new AluGroup();
AluInstr *ir = nullptr;
- assert(nir_dest_num_components(alu.dest.dest) == 1);
+ assert(alu.dest.dest.ssa.num_components == 1);
auto tmpx = value_factory.temp_register();
shader.emit_instruction(new AluInstr(op2_and_int,
auto group = new AluGroup();
AluInstr *ir = nullptr;
- assert(nir_dest_num_components(alu.dest.dest) == 1);
+ assert(alu.dest.dest.ssa.num_components == 1);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
auto src = value_factory.src(alu.src[0], i);
ir = new AluInstr(op2_and_int,
value_factory.dest(alu.dest.dest.ssa, i, pin),
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(alu.src[0], i),
auto pin = pin_for_components(alu);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(*src0, i),
auto pin = pin_for_components(alu);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(*src[0], i),
auto& value_factory = shader.value_factory();
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.zero(),
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(src0, i),
PRegister reg[4];
- int num_comp = nir_dest_num_components(alu.dest.dest);
+ int num_comp = alu.dest.dest.ssa.num_components;
for (int i = 0; i < num_comp; ++i) {
reg[i] = value_factory.temp_register();
const std::set<AluModifiers> flags({alu_write, alu_last_instr, alu_is_cayman_trans});
- for (unsigned j = 0; j < nir_dest_num_components(alu.dest.dest); ++j) {
+ for (unsigned j = 0; j < alu.dest.dest.ssa.num_components; ++j) {
unsigned ncomp = j == 3 ? 4 : 3;
AluInstr::SrcValues srcs(ncomp);
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
+ for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(src0, i),
const std::set<AluModifiers> flags({alu_write, alu_last_instr, alu_is_cayman_trans});
- for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
+ for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
AluInstr::SrcValues srcs(2 * last_slot);
PRegister dest = value_factory.dest(alu.dest.dest.ssa, k, pin_free);
{
auto& value_factory = shader.value_factory();
- int ncomp = nir_dest_num_components(alu.dest.dest);
+ int ncomp = alu.dest.dest.ssa.num_components;
RegisterVec4::Swizzle src_swz = {7, 7, 7, 7};
RegisterVec4::Swizzle tmp_swz = {7, 7, 7, 7};
for (auto i = 0; i < ncomp; ++i) {
{0, 1, 2, 3}
};
- int comp_idx = nir_dest_num_components(intr->dest) - 1;
+ int comp_idx = intr->dest.ssa.num_components - 1;
auto [offset, res_offset] = shader.evaluate_resource_offset(intr, 0);
{
if (nir_intrinsic_image_dim(intrin) == GLSL_SAMPLER_DIM_CUBE &&
nir_intrinsic_image_array(intrin) &&
- nir_dest_num_components(intrin->dest) > 2) {
+ intrin->dest.ssa.num_components > 2) {
/* Need to load the layers from a const buffer */
auto dest = vf.dest_vec4(intrin->dest.ssa, pin_group);
if (op->intrinsic == nir_intrinsic_load_shared) {
nir_def *addr = op->src[0].ssa;
- switch (nir_dest_num_components(op->dest)) {
+ switch (op->dest.ssa.num_components) {
case 2: {
auto addr2 = nir_iadd_imm(&b, addr, 4);
addr = nir_vec2(&b, addr, addr2);
auto load =
nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_local_shared_r600);
- load->num_components = nir_dest_num_components(op->dest);
+ load->num_components = op->dest.ssa.num_components;
load->src[0] = nir_src_for_ssa(addr);
nir_def_init(&load->instr, &load->dest.ssa, load->num_components,
32);
if (load_value)
default_value =
- nir_imm_zero(b, nir_dest_num_components(ir->dest), ir->dest.ssa.bit_size);
+ nir_imm_zero(b, ir->dest.ssa.num_components, ir->dest.ssa.bit_size);
auto image_exists =
nir_ult_imm(b, ir->src[0].ssa, b->shader->info.num_images);
LowerLoad64Uniform::lower(nir_instr *instr)
{
auto intr = nir_instr_as_intrinsic(instr);
- int old_components = nir_dest_num_components(intr->dest);
+ int old_components = intr->dest.ssa.num_components;
assert(old_components <= 2);
intr->dest.ssa.num_components *= 2;
intr->dest.ssa.bit_size = 32;
}
case nir_instr_type_phi: {
auto phi = nir_instr_as_phi(instr);
- return nir_dest_num_components(phi->dest) == 64;
+ return phi->dest.ssa.num_components == 64;
}
default:
return false;
case nir_intrinsic_load_ssbo:
if (intr->dest.ssa.bit_size != 64)
return false;
- return nir_dest_num_components(intr->dest) >= 3;
+ return intr->dest.ssa.num_components >= 3;
case nir_intrinsic_store_output:
if (nir_src_bit_size(intr->src[0]) != 64)
return false;
auto alu = nir_instr_as_alu(instr);
switch (alu->op) {
case nir_op_bcsel:
- if (nir_dest_num_components(alu->dest.dest) < 3)
+ if (alu->dest.dest.ssa.num_components < 3)
return false;
return alu->dest.dest.ssa.bit_size == 64;
case nir_op_bany_fnequal3:
nir_def *
LowerSplit64BitVar::split_double_load(nir_intrinsic_instr *load1)
{
- unsigned old_components = nir_dest_num_components(load1->dest);
+ unsigned old_components = load1->dest.ssa.num_components;
auto load2 = nir_instr_as_intrinsic(nir_instr_clone(b->shader, &load1->instr));
nir_io_semantics sem = nir_intrinsic_io_semantics(load1);
nir_def *
LowerSplit64BitVar::split_double_load_uniform(nir_intrinsic_instr *intr)
{
- unsigned second_components = nir_dest_num_components(intr->dest) - 2;
+ unsigned second_components = intr->dest.ssa.num_components - 2;
nir_intrinsic_instr *load2 =
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
load2->src[0] = nir_src_for_ssa(nir_iadd_imm(b, intr->src[0].ssa, 1));
nir_def *
LowerSplit64BitVar::split_double_load_ssbo(nir_intrinsic_instr *intr)
{
- unsigned second_components = nir_dest_num_components(intr->dest) - 2;
+ unsigned second_components = intr->dest.ssa.num_components - 2;
nir_intrinsic_instr *load2 =
nir_instr_as_intrinsic(nir_instr_clone(b->shader, &intr->instr));
nir_def *
LowerSplit64BitVar::split_double_load_ubo(nir_intrinsic_instr *intr)
{
- unsigned second_components = nir_dest_num_components(intr->dest) - 2;
+ unsigned second_components = intr->dest.ssa.num_components - 2;
nir_intrinsic_instr *load2 =
nir_instr_as_intrinsic(nir_instr_clone(b->shader, &intr->instr));
load2->src[0] = intr->src[0];
LowerSplit64BitVar::split_bcsel(nir_alu_instr *alu)
{
static nir_def *dest[4];
- for (unsigned i = 0; i < nir_dest_num_components(alu->dest.dest); ++i) {
+ for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; ++i) {
dest[i] = nir_bcsel(b,
nir_channel(b, alu->src[0].src.ssa, i),
nir_channel(b, alu->src[1].src.ssa, i),
nir_channel(b, alu->src[2].src.ssa, i));
}
- return nir_vec(b, dest, nir_dest_num_components(alu->dest.dest));
+ return nir_vec(b, dest, alu->dest.dest.ssa.num_components);
}
nir_def *
get_dest_usee_mask(nir_intrinsic_instr *op)
{
MaskQuery mq = {0};
- mq.full_mask = (1 << nir_dest_num_components(op->dest)) - 1;
+ mq.full_mask = (1 << op->dest.ssa.num_components) - 1;
nir_foreach_use(use_src, &op->dest.ssa)
{
auto new_load = nir_load_local_shared_r600(b, 32, addr_outer);
auto undef = nir_undef(b, 1, 32);
- int comps = nir_dest_num_components(op->dest);
+ int comps = op->dest.ssa.num_components;
nir_def *remix[4] = {undef, undef, undef, undef};
int chan = 0;
RegisterVec4::Swizzle dest_swz{7, 7, 7, 7};
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; ++i) {
dest_swz[i] = i + nir_intrinsic_component(instr);
}
int buf_cmp = nir_intrinsic_component(instr);
AluInstr *ir = nullptr;
- auto pin = nir_dest_num_components(instr->dest) == 1
+ auto pin = instr->dest.ssa.num_components == 1
? pin_free
: pin_none;
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; ++i) {
sfn_log << SfnLog::io << "UBO[" << bufid << "] " << instr->dest.ssa.index
<< " const[" << i << "]: " << instr->const_index[i] << "\n";
AluInstr *ir = nullptr;
auto kc_id = value_factory().src(instr->src[0], 0);
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; ++i) {
int cmp = buf_cmp + i;
auto u =
new UniformValue(512 + buf_offset->u32, cmp, kc_id, nir_intrinsic_base(instr));
auto location = nir_intrinsic_io_semantics(intr).location;
if (location == VARYING_SLOT_POS) {
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
ir = new AluInstr(op1_mov,
vf.dest(intr->dest.ssa, i, pin_none),
m_pos_input[i],
unsigned loc = nir_intrinsic_io_semantics(intr).location;
switch (loc) {
case VARYING_SLOT_POS:
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i)
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i)
vf.inject_value(intr->dest.ssa, i, m_pos_input[i]);
return true;
case VARYING_SLOT_FACE:
{
auto& vf = value_factory();
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
sfn_log << SfnLog::io << "Inject register "
<< *m_interpolated_inputs[nir_intrinsic_base(intr)][i] << "\n";
unsigned index = nir_intrinsic_component(intr) + i;
bool need_temp = comp > 0;
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
if (need_temp) {
auto tmp = vf.temp_register(comp + i);
ir =
ASSERTED auto param = nir_src_as_const_value(intr->src[1]);
assert(param && "Indirect PS inputs not (yet) supported");
- int dest_num_comp = nir_dest_num_components(intr->dest);
+ int dest_num_comp = intr->dest.ssa.num_components;
int start_comp = nir_intrinsic_component(intr);
bool need_temp = start_comp > 0;
if (need_temp) {
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
auto real_dst = vf.dest(intr->dest.ssa, i, pin_chan);
ir = new AluInstr(op1_mov, real_dst, dst[i + start_comp], AluInstr::write);
emit_instruction(ir);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
RegisterVec4::Swizzle dest_swz{7, 7, 7, 7};
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; ++i) {
dest_swz[i] = i + nir_intrinsic_component(instr);
}
AluInstr *ir = nullptr;
if (location < VERT_ATTRIB_MAX) {
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
auto src = vf.allocate_pinned_register(driver_location + 1, i);
src->set_flag(Register::ssa);
vf.inject_value(intr->dest.ssa, i, src);
if (instr->op == nir_op_unpack_unorm_4x8) {
struct qreg src = ntq_get_src(c, instr->src[0].src,
instr->src[0].swizzle[0]);
- unsigned count = nir_dest_num_components(instr->dest.dest);
+ unsigned count = instr->dest.dest.ssa.num_components;
for (int i = 0; i < count; i++) {
ntq_store_def(c, &instr->dest.dest.ssa, i,
qir_UNPACK_8_F(c, src, i));
}
unsigned bit_size = alu->dest.dest.ssa.bit_size;
- unsigned num_components = nir_dest_num_components(alu->dest.dest);
+ unsigned num_components = alu->dest.dest.ssa.num_components;
nir_alu_type atype = bit_size == 1 ?
nir_type_bool :
(alu_op_is_typeless(alu->op) ? typeless_type : nir_op_infos[alu->op].output_type);
emit_load_shared(struct ntv_context *ctx, nir_intrinsic_instr *intr)
{
SpvId dest_type = get_def_type(ctx, &intr->dest.ssa, nir_type_uint);
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
unsigned bit_size = intr->dest.ssa.bit_size;
SpvId uint_type = get_uvec_type(ctx, bit_size, 1);
SpvId ptr_type = spirv_builder_type_pointer(&ctx->builder,
emit_load_scratch(struct ntv_context *ctx, nir_intrinsic_instr *intr)
{
SpvId dest_type = get_def_type(ctx, &intr->dest.ssa, nir_type_uint);
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
unsigned bit_size = intr->dest.ssa.bit_size;
SpvId uint_type = get_uvec_type(ctx, bit_size, 1);
SpvId ptr_type = spirv_builder_type_pointer(&ctx->builder,
SpvId load_type = get_uvec_type(ctx, 32, 1);
/* number of components being loaded */
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
SpvId constituents[NIR_MAX_VEC_COMPONENTS * 2];
SpvId result;
SpvId result = spirv_builder_emit_load(&ctx->builder, var_type,
ctx->front_face_var);
- assert(1 == nir_dest_num_components(intr->dest));
+ assert(1 == intr->dest.ssa.num_components);
store_def(ctx, &intr->dest.ssa, result, nir_type_bool);
}
}
SpvId result = spirv_builder_emit_load(&ctx->builder, var_type, load_var);
- assert(1 == nir_dest_num_components(intr->dest));
+ assert(1 == intr->dest.ssa.num_components);
store_def(ctx, &intr->dest.ssa, result, nir_type_uint);
}
switch (type) {
case nir_type_bool:
- var_type = get_bvec_type(ctx, nir_dest_num_components(intr->dest));
+ var_type = get_bvec_type(ctx, intr->dest.ssa.num_components);
break;
case nir_type_int:
var_type = get_ivec_type(ctx, intr->dest.ssa.bit_size,
- nir_dest_num_components(intr->dest));
+ intr->dest.ssa.num_components);
break;
case nir_type_uint:
var_type = get_uvec_type(ctx, intr->dest.ssa.bit_size,
- nir_dest_num_components(intr->dest));
+ intr->dest.ssa.num_components);
break;
case nir_type_float:
var_type = get_fvec_type(ctx, intr->dest.ssa.bit_size,
- nir_dest_num_components(intr->dest));
+ intr->dest.ssa.num_components);
break;
default:
unreachable("unknown type passed");
bool use_sample = glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS ||
glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
SpvId sample = use_sample ? get_src(ctx, &intr->src[2], &atype) : 0;
- SpvId dest_type = spirv_builder_type_vector(&ctx->builder, base_type, nir_dest_num_components(intr->dest));
+ SpvId dest_type = spirv_builder_type_vector(&ctx->builder, base_type,
+ intr->dest.ssa.num_components);
SpvId result = spirv_builder_emit_image_read(&ctx->builder,
dest_type,
img, coord, 0, sample, 0, sparse);
return;
}
SpvId actual_dest_type;
- unsigned num_components = nir_dest_num_components(tex->dest);
+ unsigned num_components = tex->dest.ssa.num_components;
switch (nir_alu_type_get_base_type(tex->dest_type)) {
case nir_type_int:
actual_dest_type = get_ivec_type(ctx, 32, num_components);
/* generate new atomic deref ops for every component */
nir_def *result[4];
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
for (unsigned i = 0; i < num_components; i++) {
nir_deref_instr *deref_arr = nir_build_deref_array(b, deref_struct, offset);
nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(b->shader, op);
if (deref_var != var)
return false;
b->cursor = nir_before_instr(instr);
- nir_def *zero = nir_imm_zero(b, nir_dest_num_components(intr->dest),
+ nir_def *zero = nir_imm_zero(b, intr->dest.ssa.num_components,
intr->dest.ssa.bit_size);
if (b->shader->info.stage == MESA_SHADER_FRAGMENT) {
switch (var->data.location) {
case VARYING_SLOT_BFC0:
case VARYING_SLOT_BFC1:
/* default color is 0,0,0,1 */
- if (nir_dest_num_components(intr->dest) == 4)
+ if (intr->dest.ssa.num_components == 4)
zero = nir_vector_insert_imm(b, zero, nir_imm_float(b, 1.0), 3);
break;
default:
unsigned bit_size = glsl_base_type_get_bit_size(ret_type);
unsigned dest_size = tex->dest.ssa.bit_size;
b->cursor = nir_after_instr(&tex->instr);
- unsigned num_components = nir_dest_num_components(tex->dest);
+ unsigned num_components = tex->dest.ssa.num_components;
bool rewrite_depth = tex->is_shadow && num_components > 1 && tex->op != nir_texop_tg4 && !tex->is_sparse;
if (bit_size == dest_size && !rewrite_depth)
return NULL;
const struct glsl_type *type = glsl_without_array(var->type);
enum glsl_base_type ret_type = glsl_get_sampler_result_type(type);
bool is_int = glsl_base_type_is_integer(ret_type);
- unsigned num_components = nir_dest_num_components(tex->dest);
+ unsigned num_components = tex->dest.ssa.num_components;
if (tex->is_shadow)
tex->is_new_style_shadow = true;
nir_def *dest = rewrite_tex_dest(b, tex, var, NULL);
default:
return false;
}
- unsigned num_components = nir_dest_num_components(alu->dest.dest);
+ unsigned num_components = alu->dest.dest.ssa.num_components;
if (num_components == 1)
return false;
b->cursor = nir_before_instr(in);
b->cursor = nir_before_instr(&tex->instr);
nir_def_init(&txl->instr, &txl->dest.ssa,
- nir_dest_num_components(tex->dest),
+ tex->dest.ssa.num_components,
tex->dest.ssa.bit_size);
nir_builder_instr_insert(b, &txl->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txl->dest.ssa);
{
struct rogue_fs_build_data *fs_data = &b->shader->ctx->stage_data.fs;
- unsigned load_size = nir_dest_num_components(intr->dest);
+ unsigned load_size = intr->dest.ssa.num_components;
assert(load_size == 1); /* TODO: We can support larger load sizes. */
rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
struct pvr_pipeline_layout *pipeline_layout =
b->shader->ctx->pipeline_layout;
- ASSERTED unsigned load_size = nir_dest_num_components(intr->dest);
+ ASSERTED unsigned load_size = intr->dest.ssa.num_components;
assert(load_size == 1); /* TODO: We can support larger load sizes. */
rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
assert(nir_intrinsic_align(instr) > 0);
if (bit_size == 32 &&
nir_intrinsic_align(instr) >= 4) {
- assert(nir_dest_num_components(instr->dest) <= 4);
+ assert(instr->dest.ssa.num_components <= 4);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
fs_inst *inst =
bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
inst->size_written = instr->num_components * dispatch_width * 4;
} else {
- assert(nir_dest_num_components(instr->dest) == 1);
+ assert(instr->dest.ssa.num_components == 1);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
if (instr->dest.ssa.bit_size == 32 &&
nir_intrinsic_align(instr) >= 4) {
- assert(nir_dest_num_components(instr->dest) <= 4);
+ assert(instr->dest.ssa.num_components <= 4);
srcs[A64_LOGICAL_ARG] = brw_imm_ud(instr->num_components);
inst->dst.component_size(inst->exec_size);
} else {
const unsigned bit_size = instr->dest.ssa.bit_size;
- assert(nir_dest_num_components(instr->dest) == 1);
+ assert(instr->dest.ssa.num_components == 1);
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
srcs[A64_LOGICAL_ARG] = brw_imm_ud(bit_size);
assert(nir_intrinsic_align(instr) > 0);
if (bit_size == 32 &&
nir_intrinsic_align(instr) >= 4) {
- assert(nir_dest_num_components(instr->dest) <= 4);
+ assert(instr->dest.ssa.num_components <= 4);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
fs_inst *inst =
bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
inst->size_written = instr->num_components * dispatch_width * 4;
} else {
- assert(nir_dest_num_components(instr->dest) == 1);
+ assert(instr->dest.ssa.num_components == 1);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
case nir_intrinsic_load_scratch: {
assert(devinfo->ver >= 7);
- assert(nir_dest_num_components(instr->dest) == 1);
+ assert(instr->dest.ssa.num_components == 1);
const unsigned bit_size = instr->dest.ssa.bit_size;
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
/* Read the vector */
- assert(nir_dest_num_components(instr->dest) == 1);
+ assert(instr->dest.ssa.num_components == 1);
assert(bit_size <= 32);
assert(nir_intrinsic_align(instr) > 0);
if (bit_size == 32 &&
/* Read the first few 32-bit scalars from InlineData. */
if (nir_src_is_const(intrin->src[0]) &&
intrin->dest.ssa.bit_size == 32 &&
- nir_dest_num_components(intrin->dest) == 1) {
+ intrin->dest.ssa.num_components == 1) {
unsigned off = nir_intrinsic_base(intrin) + nir_src_as_uint(intrin->src[0]);
unsigned off_dw = off / 4;
if (off % 4 == 0 && off_dw < BRW_TASK_MESH_PUSH_CONSTANTS_SIZE_DW) {
{
assert(instr->dest.ssa.bit_size == 32);
- unsigned comps = nir_dest_num_components(instr->dest);
+ unsigned comps = instr->dest.ssa.num_components;
if (comps == 0)
return;
{
assert(instr->dest.ssa.bit_size == 32);
- unsigned comps = nir_dest_num_components(instr->dest);
+ unsigned comps = instr->dest.ssa.num_components;
if (comps == 0)
return;
/* Without the LSC, we can only do block loads of at least 4dwords (1
* oword).
*/
- if (!devinfo->has_lsc && nir_dest_num_components(intrin->dest) < 4)
+ if (!devinfo->has_lsc && intrin->dest.ssa.num_components < 4)
return false;
intrin->intrinsic =
/* Without the LSC, we can only do block loads of at least 4dwords (1
* oword).
*/
- if (!devinfo->has_lsc && nir_dest_num_components(intrin->dest) < 4)
+ if (!devinfo->has_lsc && intrin->dest.ssa.num_components < 4)
return false;
intrin->intrinsic = nir_intrinsic_load_global_constant_uniform_block_intel;
nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type |
instr->dest.dest.ssa.bit_size);
dst_reg dst = get_nir_def(instr->dest.dest.ssa, dst_type);
- dst.writemask &= nir_component_mask(nir_dest_num_components(instr->dest.dest));
+ dst.writemask &= nir_component_mask(instr->dest.dest.ssa.num_components);
src_reg op[4];
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
load_ubo(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var, unsigned offset)
{
return nir_load_ubo(b,
- nir_dest_num_components(intr->dest),
+ intr->dest.ssa.num_components,
intr->dest.ssa.bit_size,
nir_imm_int(b, var->data.binding),
nir_imm_int(b, offset),
.align_mul = 256,
.align_offset = offset,
.range_base = offset,
- .range = intr->dest.ssa.bit_size * nir_dest_num_components(intr->dest) / 8);
+ .range = intr->dest.ssa.bit_size * intr->dest.ssa.num_components / 8);
}
static bool
}
const struct glsl_type *type =
- glsl_vector_type(base_type, nir_dest_num_components(intr->dest));
+ glsl_vector_type(base_type, intr->dest.ssa.num_components);
nir_def *ptr = nir_vec2(b, nir_imm_int(b, var->data.binding),
nir_u2uN(b, intr->src[0].ssa, 32));
nir_deref_instr *deref = nir_build_deref_cast(b, ptr, nir_var_mem_ubo, type,
lower_32b_offset_load(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var)
{
unsigned bit_size = intr->dest.ssa.bit_size;
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
unsigned num_bits = num_components * bit_size;
b->cursor = nir_before_instr(&intr->instr);
load_bordercolor(nir_builder *b, nir_tex_instr *tex, const dxil_wrap_sampler_state *active_state,
const dxil_texture_swizzle_state *tex_swizzle)
{
- int ndest_comp = nir_dest_num_components(tex->dest);
+ int ndest_comp = tex->dest.ssa.num_components;
unsigned swizzle[4] = {
tex_swizzle->swizzle_r,
nir_instr_remove(instr);
} else {
b->cursor = nir_after_instr(instr);
- assert(nir_dest_num_components(intr->dest) == 1);
+ assert(intr->dest.ssa.num_components == 1);
nir_def_rewrite_uses(&intr->dest.ssa, nir_undef(b, 1, intr->dest.ssa.bit_size));
}
return true;
case nir_op_vec16:
return emit_vec(ctx, alu, nir_op_infos[alu->op].num_inputs);
case nir_op_mov: {
- assert(nir_dest_num_components(alu->dest.dest) == 1);
+ assert(alu->dest.dest.ssa.num_components == 1);
store_ssa_def(ctx, &alu->dest.dest.ssa, 0, get_src_ssa(ctx,
alu->src->src.ssa, alu->src->swizzle[0]));
return true;
unsigned first_component = nir_intrinsic_has_component(intr) ?
nir_intrinsic_component(intr) : 0;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); i++)
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; i++)
store_def(ctx, &intr->dest.ssa, i,
dxil_emit_extractval(&ctx->mod, agg, i + first_component));
return false;
assert(intr->dest.ssa.bit_size == 32);
- unsigned num_components = nir_dest_num_components(intr->dest);
+ unsigned num_components = intr->dest.ssa.num_components;
assert(num_components <= 4);
for (unsigned i = 0; i < num_components; ++i) {
const struct dxil_value *component = dxil_emit_extractval(&ctx->mod, load_result, i);
if (!dimensions)
return false;
- for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
+ for (unsigned i = 0; i < intr->dest.ssa.num_components; ++i) {
const struct dxil_value *retval = dxil_emit_extractval(&ctx->mod, dimensions, i);
store_def(ctx, &intr->dest.ssa, i, retval);
}
}
struct phi_block *vphi = ralloc(ctx->phis, struct phi_block);
- vphi->num_components = nir_dest_num_components(instr->dest);
+ vphi->num_components = instr->dest.ssa.num_components;
for (unsigned i = 0; i < vphi->num_components; ++i) {
struct dxil_instr *phi = vphi->comp[i] = dxil_emit_phi(&ctx->mod, type);
if (!sample)
return false;
- for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
+ for (unsigned i = 0; i < instr->dest.ssa.num_components; ++i) {
const struct dxil_value *retval = dxil_emit_extractval(&ctx->mod, sample, i);
store_def(ctx, &instr->dest.ssa, i, retval);
}
nir_def *load_data = nir_load_ubo(
builder,
- nir_dest_num_components(intrin->dest),
+ intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size,
nir_channel(builder, load_desc, 0),
nir_imm_int(builder, offset),
.align_mul = 256,
.align_offset = offset,
.range_base = offset,
- .range = intrin->dest.ssa.bit_size * nir_dest_num_components(intrin->dest) / 8);
+ .range = intrin->dest.ssa.bit_size * intrin->dest.ssa.num_components / 8);
nir_def_rewrite_uses(&intrin->dest.ssa, load_data);
nir_instr_remove(instr);
nir_def *offset = nir_ssa_for_src(builder, intrin->src[0], 1);
nir_def *load_data = nir_load_ubo(
builder,
- nir_dest_num_components(intrin->dest),
+ intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size,
nir_channel(builder, load_desc, 0),
nir_iadd_imm(builder, offset, base),
* since that would remove the store instruction, and would make it tricky to satisfy
* the DXIL requirements of writing all position components.
*/
- nir_def *zero = nir_imm_zero(b, nir_dest_num_components(intr->dest),
+ nir_def *zero = nir_imm_zero(b, intr->dest.ssa.num_components,
intr->dest.ssa.bit_size);
nir_def_rewrite_uses(&intr->dest.ssa, zero);
nir_instr_remove(instr);
}
#define DEFAULT_CHECKS \
- if (nir_dest_num_components(insn->dest.dest) > 1) { \
+ if (insn->dest.dest.ssa.num_components > 1) { \
ERROR("nir_alu_instr only supported with 1 component!\n"); \
return false; \
}
nir_def *zero = has_dest ? nir_imm_zero(b, 1, size) : NULL;
nir_def *zeroes[4] = {zero, zero, zero, zero};
nir_def *res =
- has_dest ? nir_vec(b, zeroes, nir_dest_num_components(intr->dest)) : NULL;
+ has_dest ? nir_vec(b, zeroes, intr->dest.ssa.num_components) : NULL;
for (unsigned i = 0; i < (*lanes); ++i) {
nir_push_if(b, nir_ieq_imm(b, lane, i));
uint32_t base = nir_intrinsic_base(instr) + nir_src_as_uint(*offset);
assert((base & 3) == 0 && "unaligned push constants");
- unsigned bits =
- instr->dest.ssa.bit_size * nir_dest_num_components(instr->dest);
+ unsigned bits = instr->dest.ssa.bit_size * instr->dest.ssa.num_components;
unsigned n = DIV_ROUND_UP(bits, 32);
assert(n <= 4);
bi_index dst = bi_def_index(&instr->dest.dest.ssa);
unsigned srcs = nir_op_infos[instr->op].num_inputs;
unsigned sz = instr->dest.dest.ssa.bit_size;
- unsigned comps = nir_dest_num_components(instr->dest.dest);
+ unsigned comps = instr->dest.dest.ssa.num_components;
unsigned src_sz = srcs > 0 ? nir_src_bit_size(instr->src[0].src) : 0;
/* Indicate scalarness */
bi_emit_split_i32(b, w, dst, res_size);
bi_emit_collect_to(
b, bi_def_index(&instr->dest.ssa), w,
- DIV_ROUND_UP(nir_dest_num_components(instr->dest) * res_size, 4));
+ DIV_ROUND_UP(instr->dest.ssa.num_components * res_size, 4));
}
/* Staging registers required by texturing in the order they appear (Valhall) */
/* Index into the packed component array */
unsigned j = 0;
unsigned comps[4] = {0};
- unsigned nr_components = nir_dest_num_components(instr->dest);
+ unsigned nr_components = instr->dest.ssa.num_components;
for (unsigned i = 0; i < nr_components; ++i) {
if (mask & BITFIELD_BIT(i)) {
}
bi_make_vec_to(b, bi_def_index(&instr->dest.ssa), unpacked, comps,
- nir_dest_num_components(instr->dest),
- instr->dest.ssa.bit_size);
+ instr->dest.ssa.num_components, instr->dest.ssa.bit_size);
}
/* Simple textures ops correspond to NIR tex or txl with LOD = 0 on 2D/cube
b, .base = rt, .src_type = nir_intrinsic_dest_type(intr));
nir_def *lowered = nir_load_converted_output_pan(
- b, nir_dest_num_components(intr->dest), intr->dest.ssa.bit_size,
- conversion, .dest_type = nir_intrinsic_dest_type(intr),
+ b, intr->dest.ssa.num_components, intr->dest.ssa.bit_size, conversion,
+ .dest_type = nir_intrinsic_dest_type(intr),
.io_semantics = nir_intrinsic_io_semantics(intr));
nir_def_rewrite_uses(&intr->dest.ssa, lowered);
return false;
unsigned compsz = intr->dest.ssa.bit_size;
- unsigned totalsz = compsz * nir_dest_num_components(intr->dest);
+ unsigned totalsz = compsz * intr->dest.ssa.num_components;
/* 8, 16, 32, 64 and 128 bit loads don't need to be lowered */
if (util_bitcount(totalsz) < 2 && totalsz <= 128)
return false;
addr = nir_iadd_imm(b, addr, loadsz / 8);
}
- assert(ncomps == nir_dest_num_components(intr->dest));
+ assert(ncomps == intr->dest.ssa.num_components);
nir_def_rewrite_uses(&intr->dest.ssa, nir_vec(b, comps, ncomps));
return true;
return;
}
- unsigned nr_components = nir_dest_num_components(instr->dest.dest);
+ unsigned nr_components = instr->dest.dest.ssa.num_components;
unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
unsigned op = 0;
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
if (is_read) {
unsigned bitsize =
- intr->dest.ssa.bit_size * nir_dest_num_components(intr->dest);
+ intr->dest.ssa.bit_size * intr->dest.ssa.num_components;
switch (bitsize) {
case 8:
ins.dest_type = ins.src_types[1] =
nir_type_uint | instr->dest.ssa.bit_size;
- ins.mask = BITFIELD_MASK(nir_dest_num_components(instr->dest));
+ ins.mask = BITFIELD_MASK(instr->dest.ssa.num_components);
emit_mir_instruction(ctx, ins);
break;
}
if (b->shader->info.stage != MESA_SHADER_FRAGMENT)
return false;
- count = nir_dest_num_components(intr->dest);
+ count = intr->dest.ssa.num_components;
break;
default:
load_sysval_from_ubo(nir_builder *b, nir_intrinsic_instr *intr, unsigned offset)
{
return nir_load_ubo(
- b, nir_dest_num_components(intr->dest), intr->dest.ssa.bit_size,
+ b, intr->dest.ssa.num_components, intr->dest.ssa.bit_size,
nir_imm_int(b, PANVK_SYSVAL_UBO_INDEX), nir_imm_int(b, offset),
.align_mul = intr->dest.ssa.bit_size / 8, .align_offset = 0,
.range_base = offset, .range = intr->dest.ssa.bit_size / 8);
return false;
b->cursor = nir_before_instr(instr);
- nir_def *ubo_load = nir_load_ubo(
- b, nir_dest_num_components(intr->dest), intr->dest.ssa.bit_size,
- nir_imm_int(b, PANVK_PUSH_CONST_UBO_INDEX), intr->src[0].ssa,
- .align_mul = intr->dest.ssa.bit_size / 8, .align_offset = 0,
- .range_base = nir_intrinsic_base(intr),
- .range = nir_intrinsic_range(intr));
+ nir_def *ubo_load =
+ nir_load_ubo(b, intr->dest.ssa.num_components, intr->dest.ssa.bit_size,
+ nir_imm_int(b, PANVK_PUSH_CONST_UBO_INDEX), intr->src[0].ssa,
+ .align_mul = intr->dest.ssa.bit_size / 8, .align_offset = 0,
+ .range_base = nir_intrinsic_base(intr),
+ .range = nir_intrinsic_range(intr));
nir_def_rewrite_uses(&intr->dest.ssa, ubo_load);
nir_instr_remove(instr);
return true;
projects / platform / upstream / mesa.git / commitdiff