#define CM_AVEODIV 0x1bc
#define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4
-#define CM_EMMC2CTL 0x1d0
-#define CM_EMMC2DIV 0x1d4
/* General bits for the CM_*CTL regs */
# define CM_ENABLE BIT(4)
.frac_bits = 8,
.tcnt_mux = 39),
- /* EMMC2 clock (only available for BCM2838) */
- [BCM2838_CLOCK_EMMC2] = REGISTER_PER_CLK(
- .name = "emmc2",
- .ctl_reg = CM_EMMC2CTL,
- .div_reg = CM_EMMC2DIV,
- .int_bits = 4,
- .frac_bits = 8,
- .tcnt_mux = 42),
-
/* General purpose (GPIO) clocks */
[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
.name = "gp0",
for (i = 0; i < asize; i++) {
desc = &clk_desc_array[i];
- if (desc->clk_register && desc->data) {
- if ((i != BCM2838_CLOCK_EMMC2) ||
- of_device_is_compatible(fw_node, "brcm,bcm2838-cprman")) {
- hws[i] = desc->clk_register(cprman, desc->data);
- }
- }
+ if (desc->clk_register && desc->data)
+ hws[i] = desc->clk_register(cprman, desc->data);
}
ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
static const struct of_device_id bcm2835_clk_of_match[] = {
{ .compatible = "brcm,bcm2835-cprman", },
- { .compatible = "brcm,bcm2838-cprman", },
{}
};
MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);