dmaengine: stm32-mdma: remove GISR1 register

GISR1 was described in a not up-to-date documentation when the stm32-mdma
driver has been developed. This register has not been added in reference
manual of STM32 SoC with MDMA, which have only 32 MDMA channels.
So remove it from stm32-mdma driver.

Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220504155322.121431-2-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 95e5831..57f0eb8 100644 (file)
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -34,7 +34,6 @@
 #include "virt-dma.h"
 
 #define STM32_MDMA_GISR0               0x0000 /* MDMA Int Status Reg 1 */
-#define STM32_MDMA_GISR1               0x0004 /* MDMA Int Status Reg 2 */
 
 /* MDMA Channel x interrupt/status register */
 #define STM32_MDMA_CISR(x)             (0x40 + 0x40 * (x)) /* x = 0..62 */
@@ -169,7 +168,7 @@
 
 #define STM32_MDMA_MAX_BUF_LEN         128
 #define STM32_MDMA_MAX_BLOCK_LEN       65536
-#define STM32_MDMA_MAX_CHANNELS                63
+#define STM32_MDMA_MAX_CHANNELS                32
 #define STM32_MDMA_MAX_REQUESTS                256
 #define STM32_MDMA_MAX_BURST           128
 #define STM32_MDMA_VERY_HIGH_PRIORITY  0x3
@@ -1324,21 +1323,11 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)
 
        /* Find out which channel generates the interrupt */
        status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
-       if (status) {
-               id = __ffs(status);
-       } else {
-               status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1);
-               if (!status) {
-                       dev_dbg(mdma2dev(dmadev), "spurious it\n");
-                       return IRQ_NONE;
-               }
-               id = __ffs(status);
-               /*
-                * As GISR0 provides status for channel id from 0 to 31,
-                * so GISR1 provides status for channel id from 32 to 62
-                */
-               id += 32;
+       if (!status) {
+               dev_dbg(mdma2dev(dmadev), "spurious it\n");
+               return IRQ_NONE;
        }
+       id = __ffs(status);
 
        chan = &dmadev->chan[id];
        if (!chan) {