drm/amdgpu: add the accelerator PCIe class
authorShiwu Zhang <shiwu.zhang@amd.com>
Tue, 23 May 2023 04:02:32 +0000 (12:02 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 16:48:57 +0000 (12:48 -0400)
Add the accelerator PCIe class and match the
class in amdgpu for 0x1002 devices of that class.

From PCI spec:
"PCI Code and ID Assignment, r1.9, sec 1, 1.19"

Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/include/amd_shared.h
include/linux/pci_ids.h

index b8a1e4571cd935597c0fd3e145d9f9d1765a69fd..8e58d187b1735b7f39075807fdf4e96b0080b83d 100644 (file)
@@ -2044,7 +2044,7 @@ static const struct pci_device_id pciidlist[] = {
          .driver_data = CHIP_IP_DISCOVERY },
 
        { PCI_DEVICE(0x1002, PCI_ANY_ID),
-         .class = AMD_ACCELERATOR_PROCESSING << 8,
+         .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
          .class_mask = 0xffffff,
          .driver_data = CHIP_IP_DISCOVERY },
 
index 0f1ca0136f50cf0fa10e90af67a682e14f18329b..25b4d7f0bd35996b4bb69d952dcb3ef2008bf57b 100644 (file)
@@ -57,7 +57,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
        /* enable virtual display */
        if (adev->asic_type != CHIP_ALDEBARAN &&
            adev->asic_type != CHIP_ARCTURUS &&
-           ((adev->pdev->class >> 8) != AMD_ACCELERATOR_PROCESSING)) {
+           ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) {
                if (adev->mode_info.num_crtc == 0)
                        adev->mode_info.num_crtc = 1;
                adev->enable_virtual_display = true;
index 57d95e2cc54bbfedecbd222d4b00ea3992bec53b..f175e65b853a001ea1bcc66d8edfd5b726cbc952 100644 (file)
@@ -27,7 +27,6 @@
 
 
 #define AMD_MAX_USEC_TIMEOUT           1000000  /* 1000 ms */
-#define AMD_ACCELERATOR_PROCESSING     0x1200   /* hardcoded pci class */
 
 /*
  * Chip flags
index 45c3d62e616d858a2532b80d58a4574dcfc4a4f2..0fbfbda3dc269e8efd712ea84f2ed54a4f2c8b08 100644 (file)
 #define PCI_CLASS_SP_DPIO              0x1100
 #define PCI_CLASS_SP_OTHER             0x1180
 
+#define PCI_BASE_CLASS_ACCELERATOR     0x12
+#define PCI_CLASS_ACCELERATOR_PROCESSING       0x1200
+
 #define PCI_CLASS_OTHERS               0xff
 
 /* Vendors and devices.  Sort key: vendor first, device next. */