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clk: socfpga: agilex: fix the parents of the psi_ref_clk
author
Dinh Nguyen
<dinguyen@kernel.org>
Tue, 13 Jul 2021 14:46:19 +0000
(09:46 -0500)
committer
Stephen Boyd
<sboyd@kernel.org>
Tue, 27 Jul 2021 00:56:21 +0000
(17:56 -0700)
The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.
Fixes:
80c6b7a0894f
("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link:
https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/socfpga/clk-agilex.c
patch
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diff --git
a/drivers/clk/socfpga/clk-agilex.c
b/drivers/clk/socfpga/clk-agilex.c
index
1cb21ea
..
9dffe9b
100644
(file)
--- a/
drivers/clk/socfpga/clk-agilex.c
+++ b/
drivers/clk/socfpga/clk-agilex.c
@@
-107,10
+107,10
@@
static const struct clk_parent_data gpio_db_free_mux[] = {
};
static const struct clk_parent_data psi_ref_free_mux[] = {
- { .fw_name = "main_pll_c
3
",
- .name = "main_pll_c
3
", },
- { .fw_name = "peri_pll_c
3
",
- .name = "peri_pll_c
3
", },
+ { .fw_name = "main_pll_c
2
",
+ .name = "main_pll_c
2
", },
+ { .fw_name = "peri_pll_c
2
",
+ .name = "peri_pll_c
2
", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",