{
uint32_t sh, mb;
- sh = SH(ctx->opcode) | (1 << shn);
- mb = (MB(ctx->opcode) << 1) | mbn;
+ sh = SH(ctx->opcode) | (shn << 5);
+ mb = MB(ctx->opcode) | (mbn << 5);
gen_rldinm(ctx, mb, 63, sh);
}
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
{
uint32_t sh, me;
- sh = SH(ctx->opcode) | (1 << shn);
- me = (MB(ctx->opcode) << 1) | men;
+ sh = SH(ctx->opcode) | (shn << 5);
+ me = MB(ctx->opcode) | (men << 5);
gen_rldinm(ctx, 0, me, sh);
}
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
{
uint32_t sh, mb;
- sh = SH(ctx->opcode) | (1 << shn);
- mb = (MB(ctx->opcode) << 1) | mbn;
+ sh = SH(ctx->opcode) | (shn << 5);
+ mb = MB(ctx->opcode) | (mbn << 5);
gen_rldinm(ctx, mb, 63 - sh, sh);
}
GEN_PPC64_R4(rldic, 0x1E, 0x04);
{
uint32_t mb;
- mb = (MB(ctx->opcode) << 1) | mbn;
+ mb = MB(ctx->opcode) | (mbn << 5);
gen_rldnm(ctx, mb, 63);
}
GEN_PPC64_R2(rldcl, 0x1E, 0x08)
{
uint32_t me;
- me = (MB(ctx->opcode) << 1) | men;
+ me = MB(ctx->opcode) | (men << 5);
gen_rldnm(ctx, 0, me);
}
GEN_PPC64_R2(rldcr, 0x1E, 0x09)
uint64_t mask;
uint32_t sh, mb;
- sh = SH(ctx->opcode) | (1 << shn);
- mb = (MB(ctx->opcode) << 1) | mbn;
+ sh = SH(ctx->opcode) | (shn << 5);
+ mb = MB(ctx->opcode) | (mbn << 5);
if (likely(sh == 0)) {
if (likely(mb == 0)) {
gen_op_load_gpr_T0(rS(ctx->opcode));
/*** Addressing modes ***/
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
-static inline void gen_addr_imm_index (DisasContext *ctx)
+static inline void gen_addr_imm_index (DisasContext *ctx, int maskl)
{
target_long simm = SIMM(ctx->opcode);
+ if (maskl)
+ simm &= ~0x03;
if (rA(ctx->opcode) == 0) {
gen_set_T0(simm);
} else {
#define GEN_LD(width, opc, type) \
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
{ \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
op_ldst(l##width); \
gen_op_store_T1_gpr(rD(ctx->opcode)); \
}
RET_INVAL(ctx); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ if (type == PPC_64B) \
+ gen_addr_imm_index(ctx, 1); \
+ else \
+ gen_addr_imm_index(ctx, 0); \
op_ldst(l##width); \
gen_op_store_T1_gpr(rD(ctx->opcode)); \
gen_op_store_T0_gpr(rA(ctx->opcode)); \
return;
}
}
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 1);
if (ctx->opcode & 0x02) {
/* lwa (lwau is undefined) */
op_ldst(lwa);
#define GEN_ST(width, opc, type) \
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
{ \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
gen_op_load_gpr_T1(rS(ctx->opcode)); \
op_ldst(st##width); \
}
RET_INVAL(ctx); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ if (type == PPC_64B) \
+ gen_addr_imm_index(ctx, 1); \
+ else \
+ gen_addr_imm_index(ctx, 0); \
gen_op_load_gpr_T1(rS(ctx->opcode)); \
op_ldst(st##width); \
gen_op_store_T0_gpr(rA(ctx->opcode)); \
return;
}
}
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 1);
gen_op_load_gpr_T1(rS(ctx->opcode));
op_ldst(std);
if (Rc(ctx->opcode))
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
op_ldstm(lmw, rD(ctx->opcode));
}
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
op_ldstm(stmw, rS(ctx->opcode));
}
RET_EXCP(ctx, EXCP_NO_FP, 0); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
op_ldst(l##width); \
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
}
RET_INVAL(ctx); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
op_ldst(l##width); \
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
gen_op_store_T0_gpr(rA(ctx->opcode)); \
RET_EXCP(ctx, EXCP_NO_FP, 0); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
op_ldst(st##width); \
}
RET_INVAL(ctx); \
return; \
} \
- gen_addr_imm_index(ctx); \
+ gen_addr_imm_index(ctx, 0); \
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
op_ldst(st##width); \
gen_op_store_T0_gpr(rA(ctx->opcode)); \
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
op_POWER2_lfq();
gen_op_store_FT0_fpr(rD(ctx->opcode));
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
op_POWER2_lfq();
gen_op_store_FT0_fpr(rD(ctx->opcode));
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
{
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
gen_op_load_fpr_FT0(rS(ctx->opcode));
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
op_POWER2_stfq();
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- gen_addr_imm_index(ctx);
+ gen_addr_imm_index(ctx, 0);
gen_op_load_fpr_FT0(rS(ctx->opcode));
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
op_POWER2_stfq();