(SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
+def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
(ADDUW GPR:$rs1, GPR:$rs2)>;
}
;
; RV64IB-LABEL: adduw:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: add.uw a0, a0, a1
+; RV64IB-NEXT: add.uw a0, a1, a0
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: adduw:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: add.uw a0, a0, a1
+; RV64IBA-NEXT: add.uw a0, a1, a0
; RV64IBA-NEXT: ret
%and = and i64 %b, 4294967295
%add = add i64 %and, %a
;
; RV64IB-LABEL: adduw_2:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: add.uw a0, a1, a0
+; RV64IB-NEXT: add.uw a0, a0, a1
; RV64IB-NEXT: lb a0, 0(a0)
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: adduw_2:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: add.uw a0, a1, a0
+; RV64IBA-NEXT: add.uw a0, a0, a1
; RV64IBA-NEXT: lb a0, 0(a0)
; RV64IBA-NEXT: ret
%3 = zext i32 %0 to i64