return pi;
}
-u32 sumo_get_xclk(struct radeon_device *rdev)
-{
- return rdev->clock.spll.reference_freq;
-}
-
static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
{
if (enable)
static void sumo_program_git(struct radeon_device *rdev)
{
u32 p, u;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
r600_calculate_u_and_p(SUMO_GICST_DFLT,
xclk, 16, &p, &u);
static void sumo_program_grsd(struct radeon_device *rdev)
{
u32 p, u;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
u32 grs = 256 * 25 / 100;
r600_calculate_u_and_p(1, xclk, 14, &p, &u);
u32 p, u;
u32 p_c, p_p, d_p;
u32 r_t, i_t;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
if (rdev->family == CHIP_PALM) {
p_c = 4;
u32 high_clk)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
pi->pasi = 65535 * 100 / high_clk;
pi->asi = 65535 * 100 / high_clk;
void sumo_program_sstp(struct radeon_device *rdev)
{
u32 p, u;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
r600_calculate_u_and_p(SUMO_SST_DFLT,
xclk, 16, &p, &u);
static void sumo_program_ttp(struct radeon_device *rdev)
{
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
u32 p, u;
u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
{
u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
u32 p, u;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
r600_calculate_u_and_p(100000,
xclk, 14, &p, &u);
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 period, unit, timer_value;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
>> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
u32 p, u;
u32 value;
struct atom_clock_dividers dividers;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
u32 sssd = 1;
int ret;
u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
u32 p, u;
u32 tp = RREG32_SMC(PM_TP);
u32 val;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
u32 p, u;
u32 tp = RREG32_SMC(PM_TP);
u32 ni;
- u32 xclk = sumo_get_xclk(rdev);
+ u32 xclk = radeon_get_xclk(rdev);
u32 value;
r600_calculate_u_and_p(400, xclk, 16, &p, &u);