-def sctof_f32:Pat < (f32 (sint_to_fp GPRI8:$src)),
-(f32
- (ITOF
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24)))) >;
-
-
def uctof_f32:Pat < (f32 (uint_to_fp GPRI8:$src)),
(f32
(UTOF
(LOADCONST_i32 24)))) >;
-def sctod_f64:Pat < (f64 (sint_to_fp GPRI8:$src)),
-(f64 (FTOD
- (ITOF
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))))) >;
-
-
def uctod_f64:Pat < (f64 (uint_to_fp GPRI8:$src)),
(f64 (FTOD
(UTOF
(LOADCONST_i32 24)),
(LOADCONST_i32 24))))) >;
-def sstof_f32:Pat < (f32 (sint_to_fp GPRI16:$src)),
-(f32
- (ITOF
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16)))) >;
-
-
def ustof_f32:Pat < (f32 (uint_to_fp GPRI16:$src)),
(f32
(UTOF
(LOADCONST_i32 16)),
(LOADCONST_i32 16)))) >;
-def sstod_f64:Pat < (f64 (sint_to_fp GPRI16:$src)),
-(f64 (FTOD
- (ITOF
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16))))) >;
-
-
def ustod_f64:Pat < (f64 (uint_to_fp GPRI16:$src)),
(f64 (FTOD
(UTOF
-def sctof_v2f32:Pat < (v2f32 (sint_to_fp GPRV2I8:$src)),
-(v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24))))) >;
-
-
def uctof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I8:$src)),
(v2f32
(UTOF_v2f32
(VCREATE_v2i32 (LOADCONST_i32 24))))) >;
-def sctod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I8:$src)),
-(v2f64
- (VINSERT_v2f64
- (VCREATE_v2f64
- (FTOD
- (VEXTRACT_v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))),
- 1)
- )),
- (FTOD
- (VEXTRACT_v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))),
- 2)
- ), 1, 256)
- ) >;
-
def uctod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I8:$src)),
(v2f64
(VINSERT_v2f64
), 1, 256)
) >;
-def sstof_v2f32:Pat < (v2f32 (sint_to_fp GPRV2I16:$src)),
-(v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16))))) >;
-
def ustof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I16:$src)),
(v2f32
(VCREATE_v2i32 (LOADCONST_i32 16))))) >;
-def sstod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I16:$src)),
-(v2f64
- (VINSERT_v2f64
- (VCREATE_v2f64
- (FTOD
- (VEXTRACT_v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))),
- 1)
- )),
- (FTOD
- (VEXTRACT_v2f32
- (ITOF_v2f32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))),
- 2)
- ), 1, 256)
- ) >;
-
def ustod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I16:$src)),
(v2f64
(VINSERT_v2f64
-def sctof_v4f32:Pat < (v4f32 (sint_to_fp GPRV4I8:$src)),
-(v4f32
- (ITOF_v4f32
- (SHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24))))) >;
-
-
def uctof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I8:$src)),
(v4f32
(UTOF_v4f32
(VCREATE_v4i32 (LOADCONST_i32 24))))) >;
-def sstof_v4f32:Pat < (v4f32 (sint_to_fp GPRV4I16:$src)),
-(v4f32
- (ITOF_v4f32
- (SHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i16 GPRV4I16:$src),
- (VCREATE_v4i32 (LOADCONST_i32 16))),
- (VCREATE_v4i32 (LOADCONST_i32 16))))) >;
-
-
def ustof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I16:$src)),
(v4f32
(UTOF_v4f32
// TODO: Implement custom UREM/SREM routines
setOperationAction(ISD::UREM, VT, Expand);
setOperationAction(ISD::SREM, VT, Expand);
- setOperationAction(ISD::SINT_TO_FP, VT, Custom);
setOperationAction(ISD::UINT_TO_FP, VT, Custom);
- setOperationAction(ISD::FP_TO_SINT, VT, Custom);
setOperationAction(ISD::FP_TO_UINT, VT, Custom);
setOperationAction(ISDBITCAST, VT, Custom);
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::Constant , MVT::i64 , Legal);
setOperationAction(ISD::UDIV, MVT::v2i64, Expand);
setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Expand);
setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);
setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
// We want to expand vector conversions into their scalar
// counterparts.
- setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Expand);
- setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Expand);
setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand);
LOWER(JumpTable);
LOWER(ConstantPool);
LOWER(ExternalSymbol);
- LOWER(FP_TO_SINT);
LOWER(FP_TO_UINT);
- LOWER(SINT_TO_FP);
LOWER(UINT_TO_FP);
LOWER(MUL);
LOWER(SUB);
}
return res;
}
-SDValue
-AMDILTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
-{
- SDValue RHS = Op.getOperand(0);
- EVT RHSVT = RHS.getValueType();
- MVT RST = RHSVT.getScalarType().getSimpleVT();
- EVT LHSVT = Op.getValueType();
- MVT LST = LHSVT.getScalarType().getSimpleVT();
- DebugLoc DL = Op.getDebugLoc();
- SDValue DST;
- const AMDILTargetMachine*
- amdtm = reinterpret_cast<const AMDILTargetMachine*>
- (&this->getTargetMachine());
- const AMDILSubtarget*
- stm = static_cast<const AMDILSubtarget*>(
- amdtm->getSubtargetImpl());
- if (RST == MVT::f64 && RHSVT.isVector()
- && stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- // We dont support vector 64bit floating point convertions.
- for (unsigned x = 0, y = RHSVT.getVectorNumElements(); x < y; ++x) {
- SDValue op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
- DL, RST, RHS, DAG.getTargetConstant(x, MVT::i32));
- op = DAG.getNode(ISD::FP_TO_SINT, DL, LST, op);
- if (!x) {
- DST = DAG.getNode(AMDILISD::VBUILD, DL, LHSVT, op);
- } else {
- DST = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, LHSVT,
- DST, op, DAG.getTargetConstant(x, MVT::i32));
- }
- }
- } else {
- if (RST == MVT::f64
- && LST == MVT::i32) {
- if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- DST = SDValue(Op.getNode(), 0);
- } else {
- DST = genf64toi32(RHS, DAG, true);
- }
- } else if (RST == MVT::f64
- && LST == MVT::i64) {
- DST = genf64toi64(RHS, DAG, true);
- } else if (RST == MVT::f64
- && (LST == MVT::i8 || LST == MVT::i16)) {
- if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- DST = DAG.getNode(ISD::TRUNCATE, DL, LHSVT, SDValue(Op.getNode(), 0));
- } else {
- SDValue ToInt = genf64toi32(RHS, DAG, true);
- DST = DAG.getNode(ISD::TRUNCATE, DL, LHSVT, ToInt);
- }
-
- } else {
- DST = SDValue(Op.getNode(), 0);
- }
- }
- return DST;
-}
SDValue
AMDILTargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
}
SDValue
-AMDILTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
-{
- SDValue RHS = Op.getOperand(0);
- EVT RHSVT = RHS.getValueType();
- MVT RST = RHSVT.getScalarType().getSimpleVT();
- EVT INTVT;
- EVT LONGVT;
- SDValue DST;
- bool isVec = RHSVT.isVector();
- DebugLoc DL = Op.getDebugLoc();
- EVT LHSVT = Op.getValueType();
- MVT LST = LHSVT.getScalarType().getSimpleVT();
- const AMDILTargetMachine*
- amdtm = reinterpret_cast<const AMDILTargetMachine*>
- (&this->getTargetMachine());
- const AMDILSubtarget*
- stm = static_cast<const AMDILSubtarget*>(
- amdtm->getSubtargetImpl());
- if (LST == MVT::f64 && LHSVT.isVector()
- && stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- // We dont support vector 64bit floating point convertions.
- for (unsigned x = 0, y = LHSVT.getVectorNumElements(); x < y; ++x) {
- SDValue op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
- DL, RST, RHS, DAG.getTargetConstant(x, MVT::i32));
- op = DAG.getNode(ISD::UINT_TO_FP, DL, LST, op);
- if (!x) {
- DST = DAG.getNode(AMDILISD::VBUILD, DL, LHSVT, op);
- } else {
- DST = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, LHSVT, DST,
- op, DAG.getTargetConstant(x, MVT::i32));
- }
-
- }
- } else {
-
- if (isVec) {
- LONGVT = EVT(MVT::getVectorVT(MVT::i64,
- RHSVT.getVectorNumElements()));
- INTVT = EVT(MVT::getVectorVT(MVT::i32,
- RHSVT.getVectorNumElements()));
- } else {
- LONGVT = EVT(MVT::i64);
- INTVT = EVT(MVT::i32);
- }
- MVT RST = RHSVT.getScalarType().getSimpleVT();
- if ((RST == MVT::i32 || RST == MVT::i64)
- && LST == MVT::f64) {
- if (RST == MVT::i32) {
- if (stm->device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
- DST = SDValue(Op.getNode(), 0);
- return DST;
- }
- }
- SDValue c31 = DAG.getConstant( 31, INTVT );
- SDValue cSbit = DAG.getConstant( 0x80000000, INTVT );
-
- SDValue S; // Sign, as 0 or -1
- SDValue Sbit; // Sign bit, as one bit, MSB only.
- if (RST == MVT::i32) {
- Sbit = DAG.getNode( ISD::AND, DL, INTVT, RHS, cSbit );
- S = DAG.getNode(ISD::SRA, DL, RHSVT, RHS, c31 );
- } else { // 64-bit case... SRA of 64-bit values is slow
- SDValue hi = DAG.getNode( (isVec) ? AMDILISD::LCOMPHI2 : AMDILISD::LCOMPHI, DL, INTVT, RHS );
- Sbit = DAG.getNode( ISD::AND, DL, INTVT, hi, cSbit );
- SDValue temp = DAG.getNode( ISD::SRA, DL, INTVT, hi, c31 );
- S = DAG.getNode( (isVec) ? AMDILISD::LCREATE2 : AMDILISD::LCREATE, DL, RHSVT, temp, temp );
- }
-
- // get abs() of input value, given sign as S (0 or -1)
- // SpI = RHS + S
- SDValue SpI = DAG.getNode(ISD::ADD, DL, RHSVT, RHS, S);
- // SpIxS = SpI ^ S
- SDValue SpIxS = DAG.getNode(ISD::XOR, DL, RHSVT, SpI, S);
-
- // Convert unsigned value to double precision
- SDValue R;
- if (RST == MVT::i32) {
- // r = cast_u32_to_f64(SpIxS)
- R = genu32tof64(SpIxS, LHSVT, DAG);
- } else {
- // r = cast_u64_to_f64(SpIxS)
- R = genu64tof64(SpIxS, LHSVT, DAG);
- }
-
- // drop in the sign bit
- SDValue t = DAG.getNode( AMDILISD::BITCONV, DL, LONGVT, R );
- SDValue thi = DAG.getNode( (isVec) ? AMDILISD::LCOMPHI2 : AMDILISD::LCOMPHI, DL, INTVT, t );
- SDValue tlo = DAG.getNode( (isVec) ? AMDILISD::LCOMPLO2 : AMDILISD::LCOMPLO, DL, INTVT, t );
- thi = DAG.getNode( ISD::OR, DL, INTVT, thi, Sbit );
- t = DAG.getNode( (isVec) ? AMDILISD::LCREATE2 : AMDILISD::LCREATE, DL, LONGVT, tlo, thi );
- DST = DAG.getNode( AMDILISD::BITCONV, DL, LHSVT, t );
- } else {
- DST = SDValue(Op.getNode(), 0);
- }
- }
- return DST;
-}
-SDValue
AMDILTargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const
{
SDValue LHS = Op.getOperand(0);
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