#define OVC_REGRWBITS_OVADD (1 << 2)
#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
/*sprite update fields*/
-#define SPRITE_UPDATE_SURFACE (0x00000001UL)
-#define SPRITE_UPDATE_CONTROL (0x00000002UL)
-#define SPRITE_UPDATE_POSITION (0x00000004UL)
-#define SPRITE_UPDATE_SIZE (0x00000008UL)
-#define SPRITE_UPDATE_ALL (0x0000000fUL)
+#define SPRITE_UPDATE_SURFACE (0x00000001UL)
+#define SPRITE_UPDATE_CONTROL (0x00000002UL)
+#define SPRITE_UPDATE_POSITION (0x00000004UL)
+#define SPRITE_UPDATE_SIZE (0x00000008UL)
+#define SPRITE_UPDATE_WAIT_VBLANK (0X00000010UL)
+#define SPRITE_UPDATE_ALL (0x0000001fUL)
struct intel_sprite_context {
uint32_t update_mask;
UHBUsage usage =
arg->b_force_hw_on ? OSPM_UHB_FORCE_POWER_ON : OSPM_UHB_ONLY_IF_ON;
uint32_t ovadd;
+ int retry;
if (arg->sprite_context_mask & REGRWBITS_SPRITE_UPDATE) {
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage))
else
return -EINVAL;
+ if ((arg->sprite_context.update_mask &
+ SPRITE_UPDATE_WAIT_VBLANK)) {
+ /**
+ * wait for vblank upto 30ms,the period of vblank is 22ms.
+ */
+ retry = 3000;
+ while (--retry) {
+ if ((PSB_RVDC32(PIPEASTAT + reg_offset) &
+ PIPE_VBLANK_STATUS))
+ break;
+ udelay(10);
+ }
+ }
+
if ((arg->sprite_context.update_mask & SPRITE_UPDATE_POSITION))
PSB_WVDC32(arg->sprite_context.pos,
DSPAPOS + reg_offset);
DSPASTRIDE + reg_offset);
}
+ if ((arg->sprite_context.update_mask & SPRITE_UPDATE_CONTROL)) {
+ PSB_WVDC32(arg->sprite_context.cntr,
+ DSPACNTR + reg_offset);
+ }
+
if ((arg->sprite_context.update_mask & SPRITE_UPDATE_SURFACE)) {
PSB_WVDC32(arg->sprite_context.linoff,
DSPALINOFF + reg_offset);
DSPASURF + reg_offset);
}
- if ((arg->sprite_context.update_mask & SPRITE_UPDATE_CONTROL)) {
- PSB_WVDC32(arg->sprite_context.cntr,
- DSPACNTR + reg_offset);
- PSB_WVDC32(PSB_RVDC32(DSPASURF + reg_offset),
- DSPASURF + reg_offset);
- }
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}