clk: armada-370-xp: add support for clock framework
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Sat, 17 Nov 2012 14:22:24 +0000 (15:22 +0100)
committerThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 20 Nov 2012 13:46:48 +0000 (14:46 +0100)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>

arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-xp-mv78230.dtsi
arch/arm/boot/dts/armada-xp-mv78260.dtsi
arch/arm/boot/dts/armada-xp-mv78460.dtsi
arch/arm/boot/dts/armada-xp.dtsi
arch/arm/mach-mvebu/Kconfig
arch/arm/mach-mvebu/armada-370-xp.c

index 2069151..175df28 100644 (file)
                        #interrupts-cells = <2>;
                        interrupts = <91>;
                };
+
+               coreclk: mvebu-sar@d0018230 {
+                       compatible = "marvell,armada-370-core-clock";
+                       reg = <0xd0018230 0x08>;
+                       #clock-cells = <1>;
+               };
+
+               gateclk: clock-gating-control@d0018220 {
+                       compatible = "marvell,armada-370-gating-clock";
+                       reg = <0xd0018220 0x4>;
+                       clocks = <&coreclk 0>;
+                       #clock-cells = <1>;
+               };
+
+
        };
 };
index ea35519..c45c7b4 100644 (file)
                gpio1 = &gpio1;
        };
 
+       cpus {
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           cpu@0 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <0>;
+               clocks = <&cpuclk 0>;
+           };
+       }
+
        soc {
                pinctrl {
                        compatible = "marvell,mv78230-pinctrl";
index 2057863..a2aee57 100644 (file)
                gpio2 = &gpio2;
        };
 
+       cpus {
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           cpu@0 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <0>;
+               clocks = <&cpuclk 0>;
+           };
+
+           cpu@1 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <1>;
+               clocks = <&cpuclk 1>;
+           };
+       };
+
        soc {
                pinctrl {
                        compatible = "marvell,mv78260-pinctrl";
index ffac983..da03a12 100644 (file)
                gpio2 = &gpio2;
        };
 
+
+       cpus {
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           cpu@0 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <0>;
+               clocks = <&cpuclk 0>;
+           };
+
+           cpu@1 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <1>;
+               clocks = <&cpuclk 1>;
+           };
+
+           cpu@2 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <2>;
+               clocks = <&cpuclk 2>;
+           };
+
+           cpu@3 {
+               device_type = "cpu";
+               compatible = "marvell,sheeva-v7";
+               reg = <3>;
+               clocks = <&cpuclk 3>;
+           };
+       };
+
        soc {
                pinctrl {
                        compatible = "marvell,mv78460-pinctrl";
index 71d6b5d..f51554e 100644 (file)
                                marvell,timer-25Mhz;
                };
 
+               coreclk: mvebu-sar@d0018230 {
+                       compatible = "marvell,armada-xp-core-clock";
+                       reg = <0xd0018230 0x08>;
+                       #clock-cells = <1>;
+               };
+
+               cpuclk: clock-complex@d0018700 {
+                       #clock-cells = <1>;
+                       compatible = "marvell,armada-xp-cpu-clock";
+                       reg = <0xd0018700 0xA0>;
+                       clocks = <&coreclk 1>;
+               };
+
+               gateclk: clock-gating-control@d0018220 {
+                       compatible = "marvell,armada-xp-gating-clock";
+                       reg = <0xd0018220 0x4>;
+                       clocks = <&coreclk 0>;
+                       #clock-cells = <1>;
+               };
+
                system-controller@d0018200 {
                                compatible = "marvell,armada-370-xp-system-controller";
                                reg = <0xd0018200 0x500>;
index 416d46e..79299cd 100644 (file)
@@ -9,6 +9,10 @@ config ARCH_MVEBU
        select PINCTRL
        select PLAT_ORION
        select SPARSE_IRQ
+       select CLKDEV_LOOKUP
+       select MVEBU_CLK_CORE
+       select MVEBU_CLK_CPU
+       select MVEBU_CLK_GATING
 
 if ARCH_MVEBU
 
index 49d7915..3292d6d 100644 (file)
@@ -17,6 +17,7 @@
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/time-armada-370-xp.h>
+#include <linux/clk/mvebu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -37,8 +38,14 @@ void __init armada_370_xp_map_io(void)
        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
 }
 
+void __init armada_370_xp_timer_and_clk_init(void)
+{
+       mvebu_clocks_init();
+       armada_370_xp_timer_init();
+}
+
 struct sys_timer armada_370_xp_timer = {
-       .init           = armada_370_xp_timer_init,
+       .init           = armada_370_xp_timer_and_clk_init,
 };
 
 static void __init armada_370_xp_dt_init(void)