si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
+ si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
S_02800C_NOOP_CULL_DISABLE(1));
}
+ if (info->count_from_stream_output) {
+ struct r600_so_target *t =
+ (struct r600_so_target*)info->count_from_stream_output;
+ uint64_t va = r600_resource_va(&rctx->screen->b.b,
+ &t->buf_filled_size->b.b);
+ va += t->buf_filled_size_offset;
+
+ si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
+ t->stride_in_dw);
+
+ si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
+ si_pm4_cmd_add(pm4,
+ COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
+ COPY_DATA_DST_SEL(COPY_DATA_REG) |
+ COPY_DATA_WR_CONFIRM);
+ si_pm4_cmd_add(pm4, va); /* src address lo */
+ si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
+ si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
+ si_pm4_cmd_add(pm4, 0); /* unused */
+ si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+ si_pm4_cmd_end(pm4, true);
+ }
+
/* draw packet */
si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
if (ib->index_size == 4) {
#define WAIT_REG_MEM_EQUAL 3
#define PKT3_MEM_WRITE 0x3D /* not on CIK */
#define PKT3_INDIRECT_BUFFER 0x32
+#define PKT3_COPY_DATA 0x40
+#define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
+#define COPY_DATA_REG 0
+#define COPY_DATA_MEM 1
+#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8)
+#define COPY_DATA_WR_CONFIRM (1 << 20)
#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */
#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
#define PKT3_COND_WRITE 0x45