Merge branch 'pci/iommu'

- Allow PASID on fake PCIe devices, e.g., HiSilicon KunPeng920 and
  KunPeng930 AMBA devices, without TLP prefixes (Zhangfei Gao)

- Allow SVA / dma-can-stall on fake PCIe devices (Zhangfei Gao)

* pci/iommu:
  PCI: Set dma-can-stall for HiSilicon chips
  PCI: Allow PASID on fake PCIe devices without TLP prefixes

diff --combined drivers/pci/quirks.c
index 664233c2ef29c41d232845569c1c442ccaf71f0a,1871c1de4e750da0bee534e7754a55e4a7102d00..0b5eace979fc11e8aaca28e23b3e40ca2435ca9d
--- 1/drivers/pci/quirks.c
--- 2/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@@ -1821,6 -1821,45 +1821,45 @@@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_I
  
  DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
  
+ /*
+  * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
+  * actually on the AMBA bus. These fake PCI devices can support SVA via
+  * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
+  *
+  * Normally stalling must not be enabled for PCI devices, since it would
+  * break the PCI requirement for free-flowing writes and may lead to
+  * deadlock.  We expect PCI devices to support ATS and PRI if they want to
+  * be fault-tolerant, so there's no ACPI binding to describe anything else,
+  * even when a "PCI" device turns out to be a regular old SoC device
+  * dressed up as a RCiEP and normal rules don't apply.
+  */
+ static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
+ {
+       struct property_entry properties[] = {
+               PROPERTY_ENTRY_BOOL("dma-can-stall"),
+               {},
+       };
+ 
+       if (pdev->revision != 0x21 && pdev->revision != 0x30)
+               return;
+ 
+       pdev->pasid_no_tlp = 1;
+ 
+       /*
+        * Set the dma-can-stall property on ACPI platforms. Device tree
+        * can set it directly.
+        */
+       if (!pdev->dev.of_node &&
+           device_add_properties(&pdev->dev, properties))
+               pci_warn(pdev, "could not add stall property");
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
+ 
  /*
   * It's possible for the MSI to get corrupted if SHPC and ACPI are used
   * together on certain PXH-based systems.
@@@ -3234,13 -3273,12 +3273,13 @@@ static void fixup_mpss_256(struct pci_d
  {
        dev->pcie_mpss = 1; /* 256 bytes */
  }
 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
 -                       PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
 -                       PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
 -                       PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
 +                      PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
 +                      PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
 +                      PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
  
  /*
   * Intel 5000 and 5100 Memory controllers have an erratum with read completion