#include <asm/hardware.h>
#define S5P_ADDR_BASE (0xe0000000)
-
#define S5P_ADDR(x) (S5P_ADDR_BASE + (x))
#define S5P_PA_ID S5P_ADDR(0x00000000) /* ID Base */
#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */
#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */
#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */
-#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */
-#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Interrupt Controller 0 */
-#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Interrupt Controller 1 */
-#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Interrupt Controller 3 */
-#define S5P_PA_SROM S5P_ADDR(0x07000000) /* SROM */
-#define S5P_PA_ONENAND S5P_ADDR(0x07100000) /* ONENAND */
-#define S5P_PA_NAND S5P_ADDR(0x07200000) /* NAND */
-#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */
-#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */
+#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */
+#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt Controller 0 */
+#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt Controller 1 */
+#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt Controller 2 */
+#define S5P_PA_TZIC0 S5P_ADDR(0x05000000) /* TrustZone Interrupt Controller 0 */
+#define S5P_PA_TZIC1 S5P_ADDR(0x05100000) /* TrustZone Interrupt Controller 1 */
+#define S5P_PA_TZIC2 S5P_ADDR(0x05200000) /* TrustZone Interrupt Controller 2 */
+#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */
+#define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */
+#define S5P_PA_ONENANDC S5P_ADDR(0x07100000) /* OneNand Controller */
+#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */
+#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */
#define S5P_PA_SYSTEM S5P_ADDR(0x0a100000) /* System Timer */
#define S5P_PA_RTC S5P_ADDR(0x0a300000) /* RTC */
#define S5P_PA_UART S5P_ADDR(0x0c000000) /* Uart Base */
/*
- * Interrupt
+ * Vector Interrupt Controller
* : VIC0, VIC1, VIC2
*/
#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Interrupt Controller 0 */
#define S5P_VIC0_VECT_PRIO_BASE(x) (S5P_PA_VIC0 + 0x200 + (x))
#define S5P_VIC0_ADDRESS_BASE(x) (S5P_PA_VIC0 + 0xf00 + (x))
-#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
-#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
-#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
-#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */
-#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
-#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
-#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
-#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
-#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */
-#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
-#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
-
-#define S5P_VIC0IRQSTATUS S5P_VIC0_BASE(IRQSTATUS_OFFSET)
-#define S5P_VIC0FIQSTATUS S5P_VIC0_BASE(FIQSTATUS_OFFSET)
-#define S5P_VIC0RAWINTR S5P_VIC0_BASE(RAWINTR_OFFSET)
-#define S5P_VIC0INTSELECT S5P_VIC0_BASE(INTSELECT_OFFSET)
-#define S5P_VIC0INTENABLE S5P_VIC0_BASE(INTENABLE_OFFSET)
-#define S5P_VIC0INTENCLEAR S5P_VIC0_BASE(INTENCLEAR_OFFSET)
-#define S5P_VIC0SOFTINT S5P_VIC0_BASE(SOFTINT_OFFSET)
-#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(SOFTINTCLEAR_OFFSET)
-#define S5P_VIC0PROTECTION S5P_VIC0_BASE(PROTECTION_OFFSET)
-#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(SWPRIORITYMASK_OFFSET)
-#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(PRIORITYDAISY_OFFSET)
+/* Vector Interrupt Offset */
+#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
+#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
+#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
+#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */
+#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
+#define VIC_INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
+#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
+#define VIC_SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
+#define VIC_PROTECTION_OFFSET 0x20 /* Protection Enable Register */
+#define VIC_SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
+#define VIC_PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
+
+#define S5P_VIC0IRQSTATUS S5P_VIC0_BASE(VIC_IRQSTATUS_OFFSET)
+#define S5P_VIC0FIQSTATUS S5P_VIC0_BASE(VIC_FIQSTATUS_OFFSET)
+#define S5P_VIC0RAWINTR S5P_VIC0_BASE(VIC_RAWINTR_OFFSET)
+#define S5P_VIC0INTSELECT S5P_VIC0_BASE(VIC_INTSELECT_OFFSET)
+#define S5P_VIC0INTENABLE S5P_VIC0_BASE(VIC_INTENABLE_OFFSET)
+#define S5P_VIC0INTENCLEAR S5P_VIC0_BASE(VIC_INTENCLEAR_OFFSET)
+#define S5P_VIC0SOFTINT S5P_VIC0_BASE(VIC_SOFTINT_OFFSET)
+#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(VIC_SOFTINTCLEAR_OFFSET)
+#define S5P_VIC0PROTECTION S5P_VIC0_BASE(VIC_PROTECTION_OFFSET)
+#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(VIC_SWPRIORITYMASK_OFFSET)
+#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(VIC_PRIORITYDAISY_OFFSET)
#define S5P_VIC0VECTADDR0 S5P_VIC0_VECT_ADDR_BASE(0x00)
#define S5P_VIC0VECTADDR1 S5P_VIC0_VECT_ADDR_BASE(0x04)
#define S5P_VIC1_VECT_PRIO_BASE(x) (S5P_PA_VIC1 + 0x200 + (x))
#define S5P_VIC1_ADDRESS_BASE(x) (S5P_PA_VIC1 + 0xf00 + (x))
-#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
-#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
-#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
-#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */
-#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
-#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
-#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
-#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
-#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */
-#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
-#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
-
-#define S5P_VIC1IRQSTATUS S5P_VIC1_BASE(IRQSTATUS_OFFSET)
-#define S5P_VIC1FIQSTATUS S5P_VIC1_BASE(FIQSTATUS_OFFSET)
-#define S5P_VIC1RAWINTR S5P_VIC1_BASE(RAWINTR_OFFSET)
-#define S5P_VIC1INTSELECT S5P_VIC1_BASE(INTSELECT_OFFSET)
-#define S5P_VIC1INTENABLE S5P_VIC1_BASE(INTENABLE_OFFSET)
-#define S5P_VIC1INTENCLEAR S5P_VIC1_BASE(INTENCLEAR_OFFSET)
-#define S5P_VIC1SOFTINT S5P_VIC1_BASE(SOFTINT_OFFSET)
-#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(SOFTINTCLEAR_OFFSET)
-#define S5P_VIC1PROTECTION S5P_VIC1_BASE(PROTECTION_OFFSET)
-#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(SWPRIORITYMASK_OFFSET)
-#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(PRIORITYDAISY_OFFSET)
+//#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
+//#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
+//#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
+//#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */
+//#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
+//#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
+//#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
+//#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
+//#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */
+//#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
+//#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
+
+#define S5P_VIC1IRQSTATUS S5P_VIC1_BASE(VIC_IRQSTATUS_OFFSET)
+#define S5P_VIC1FIQSTATUS S5P_VIC1_BASE(VIC_FIQSTATUS_OFFSET)
+#define S5P_VIC1RAWINTR S5P_VIC1_BASE(VIC_RAWINTR_OFFSET)
+#define S5P_VIC1INTSELECT S5P_VIC1_BASE(VIC_INTSELECT_OFFSET)
+#define S5P_VIC1INTENABLE S5P_VIC1_BASE(VIC_INTENABLE_OFFSET)
+#define S5P_VIC1INTENCLEAR S5P_VIC1_BASE(VIC_INTENCLEAR_OFFSET)
+#define S5P_VIC1SOFTINT S5P_VIC1_BASE(VIC_SOFTINT_OFFSET)
+#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(VIC_SOFTINTCLEAR_OFFSET)
+#define S5P_VIC1PROTECTION S5P_VIC1_BASE(VIC_PROTECTION_OFFSET)
+#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(VIC_SWPRIORITYMASK_OFFSET)
+#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(VIC_PRIORITYDAISY_OFFSET)
#define S5P_VIC1VECTADDR0 S5P_VIC1_VECT_ADDR_BASE(0x00)
#define S5P_VIC1VECTADDR1 S5P_VIC1_VECT_ADDR_BASE(0x04)
#define S5P_VIC2_VECT_PRIO_BASE(x) (S5P_PA_VIC2 + 0x200 + (x))
#define S5P_VIC2_ADDRESS_BASE(x) (S5P_PA_VIC2 + 0xf00 + (x))
-#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
-#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
-#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
-#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */
-#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
-#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
-#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
-#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
-#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */
-#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
-#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
-
-#define S5P_VIC2IRQSTATUS S5P_VIC2_BASE(IRQSTATUS_OFFSET)
-#define S5P_VIC2FIQSTATUS S5P_VIC2_BASE(FIQSTATUS_OFFSET)
-#define S5P_VIC2RAWINTR S5P_VIC2_BASE(RAWINTR_OFFSET)
-#define S5P_VIC2INTSELECT S5P_VIC2_BASE(INTSELECT_OFFSET)
-#define S5P_VIC2INTENABLE S5P_VIC2_BASE(INTENABLE_OFFSET)
-#define S5P_VIC2INTENCLEAR S5P_VIC2_BASE(INTENCLEAR_OFFSET)
-#define S5P_VIC2SOFTINT S5P_VIC2_BASE(SOFTINT_OFFSET)
-#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(SOFTINTCLEAR_OFFSET)
-#define S5P_VIC2PROTECTION S5P_VIC2_BASE(PROTECTION_OFFSET)
-#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(SWPRIORITYMASK_OFFSET)
-#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(PRIORITYDAISY_OFFSET)
+//#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
+//#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
+//#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
+//#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */
+//#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
+//#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
+//#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
+//#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
+//#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */
+//#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
+//#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */
+
+#define S5P_VIC2IRQSTATUS S5P_VIC2_BASE(VIC_IRQSTATUS_OFFSET)
+#define S5P_VIC2FIQSTATUS S5P_VIC2_BASE(VIC_FIQSTATUS_OFFSET)
+#define S5P_VIC2RAWINTR S5P_VIC2_BASE(VIC_RAWINTR_OFFSET)
+#define S5P_VIC2INTSELECT S5P_VIC2_BASE(VIC_INTSELECT_OFFSET)
+#define S5P_VIC2INTENABLE S5P_VIC2_BASE(VIC_INTENABLE_OFFSET)
+#define S5P_VIC2INTENCLEAR S5P_VIC2_BASE(VIC_INTENCLEAR_OFFSET)
+#define S5P_VIC2SOFTINT S5P_VIC2_BASE(VIC_SOFTINT_OFFSET)
+#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(VIC_SOFTINTCLEAR_OFFSET)
+#define S5P_VIC2PROTECTION S5P_VIC2_BASE(VIC_PROTECTION_OFFSET)
+#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(VIC_SWPRIORITYMASK_OFFSET)
+#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(VIC_PRIORITYDAISY_OFFSET)
#define S5P_VIC2VECTADDR0 S5P_VIC2_VECT_ADDR_BASE(0x00)
#define S5P_VIC2VECTADDR1 S5P_VIC2_VECT_ADDR_BASE(0x04)
+/*
+ * TrustZone Interrupt Controller
+ * : TZI0, TZI1, TZI2
+ */
+#define S5P_TZIC0_BASE(x) (S5P_PA_TZIC0 + (x))
+#define S5P_TZIC1_BASE(x) (S5P_PA_TZIC1 + (x))
+#define S5P_TZIC2_BASE(x) (S5P_PA_TZIC2 + (x))
+
+#define FIQSTATUS_OFFSET (0x00) /* FIQ Status Regieter */
+#define RAWINTR_OFFSET (0x04) /* Raw Interrupt Status Register */
+#define INTSELECT_OFFSET (0x08) /* Interrupt Select Register */
+#define FIQENABLE_OFFSET (0x0c) /* FIQ Enable Register */
+#define FIQENCLEAR_OFFSET (0x10) /* FIQ Enable Clear Register */
+#define FIQBYPASS_OFFSET (0x14) /* FIQ Bypass Register */
+#define FIQPROTECTION_OFFSET (0x18) /* Protection Register */
+#define FIQLOCK_OFFSET (0x1c) /* Lock Enable Register */
+#define FIQLOCKSTATUS_OFFSET (0x20) /* Lock Status Register */
+#define PERIPHID0_OFFSET (0xfe0) /* Peripheral Identification Register */
+#define PCELLID0_OFFSET (0xff0) /* PrimeCell Identification Register */
+
+/* TZI0 */
+#define S5P_TZIC0FIQSTATUS S5P_TZIC0_BASE(FIQSTATUS_OFFSET)
+#define S5P_TZIC0RAWINTR S5P_TZIC0_BASE(RAQINTR_OFFSET)
+#define S5P_TZIC0INTSELECT S5P_TZIC0_BASE(INTSELECT_OFFSET)
+#define S5P_TZIC0FIQENABLE S5P_TZIC0_BASE(FIQENABLE_OFFSET)
+#define S5P_TZIC0FIQENCLEAR S5P_TZIC0_BASE(FIQENCLEAR_OFFSET)
+#define S5P_TZIC0FIQBYPASS S5P_TZIC0_BASE(FIQBYPASS_OFFSET)
+#define S5P_TZIC0FIQPROTECTION S5P_TZIC0_BASE(FIQPROTECTION_OFFSET)
+#define S5P_TZIC0FIQLOCK S5P_TZIC0_BASE(FIQLOCKSTATUS_OFFSET)
+#define S5P_TZIC0FIQLOCKSTATUS S5P_TZIC0_BASE(PCELLID0_OFFSET)
+
+#define S5P_TZIC0PERIPHID0 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x0)
+#define S5P_TZIC0PERIPHID1 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x4)
+#define S5P_TZIC0PERIPHID2 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x8)
+#define S5P_TZIC0PERIPHID3 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0xc)
+
+#define S5P_TZIC0PCELLID0 S5P_TZIC0_BASE(PCELLID0_OFFSET + 0x0)
+#define S5P_TZIC0PCELLID1 S5P_TZIC0_BASE(PCELLID1_OFFSET + 0x0)
+#define S5P_TZIC0PCELLID2 S5P_TZIC0_BASE(PCELLID2_OFFSET + 0x0)
+#define S5P_TZIC0PCELLID3 S5P_TZIC0_BASE(PCELLID3_OFFSET + 0x0)
+
+/* TZI1 */
+#define S5P_TZIC1FIQSTATUS S5P_TZIC1_BASE(FIQSTATUS_OFFSET)
+#define S5P_TZIC1RAWINTR S5P_TZIC1_BASE(RAQINTR_OFFSET)
+#define S5P_TZIC1INTSELECT S5P_TZIC1_BASE(INTSELECT_OFFSET)
+#define S5P_TZIC1FIQENABLE S5P_TZIC1_BASE(FIQENABLE_OFFSET)
+#define S5P_TZIC1FIQENCLEAR S5P_TZIC1_BASE(FIQENCLEAR_OFFSET)
+#define S5P_TZIC1FIQBYPASS S5P_TZIC1_BASE(FIQBYPASS_OFFSET)
+#define S5P_TZIC1FIQPROTECTION S5P_TZIC1_BASE(FIQPROTECTION_OFFSET)
+#define S5P_TZIC1FIQLOCK S5P_TZIC1_BASE(FIQLOCKSTATUS_OFFSET)
+#define S5P_TZIC1FIQLOCKSTATUS S5P_TZIC1_BASE(PCELLID0_OFFSET)
+
+#define S5P_TZIC1PERIPHID0 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x0)
+#define S5P_TZIC1PERIPHID1 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x4)
+#define S5P_TZIC1PERIPHID2 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x8)
+#define S5P_TZIC1PERIPHID3 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0xc)
+
+#define S5P_TZIC1PCELLID0 S5P_TZIC1_BASE(PCELLID0_OFFSET + 0x0)
+#define S5P_TZIC1PCELLID1 S5P_TZIC1_BASE(PCELLID1_OFFSET + 0x0)
+#define S5P_TZIC1PCELLID2 S5P_TZIC1_BASE(PCELLID2_OFFSET + 0x0)
+#define S5P_TZIC1PCELLID3 S5P_TZIC1_BASE(PCELLID3_OFFSET + 0x0)
+
+/* TZI2 */
+#define S5P_TZIC2FIQSTATUS S5P_TZIC2_BASE(FIQSTATUS_OFFSET)
+#define S5P_TZIC2RAWINTR S5P_TZIC2_BASE(RAQINTR_OFFSET)
+#define S5P_TZIC2INTSELECT S5P_TZIC2_BASE(INTSELECT_OFFSET)
+#define S5P_TZIC2FIQENABLE S5P_TZIC2_BASE(FIQENABLE_OFFSET)
+#define S5P_TZIC2FIQENCLEAR S5P_TZIC2_BASE(FIQENCLEAR_OFFSET)
+#define S5P_TZIC2FIQBYPASS S5P_TZIC2_BASE(FIQBYPASS_OFFSET)
+#define S5P_TZIC2FIQPROTECTION S5P_TZIC2_BASE(FIQPROTECTION_OFFSET)
+#define S5P_TZIC2FIQLOCK S5P_TZIC2_BASE(FIQLOCKSTATUS_OFFSET)
+#define S5P_TZIC2FIQLOCKSTATUS S5P_TZIC2_BASE(PCELLID0_OFFSET)
+
+#define S5P_TZIC2PERIPHID0 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x0)
+#define S5P_TZIC2PERIPHID1 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x4)
+#define S5P_TZIC2PERIPHID2 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x8)
+#define S5P_TZIC2PERIPHID3 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0xc)
+
+#define S5P_TZIC2PCELLID0 S5P_TZIC2_BASE(PCELLID0_OFFSET + 0x0)
+#define S5P_TZIC2PCELLID1 S5P_TZIC2_BASE(PCELLID1_OFFSET + 0x0)
+#define S5P_TZIC2PCELLID2 S5P_TZIC2_BASE(PCELLID2_OFFSET + 0x0)
+#define S5P_TZIC2PCELLID3 S5P_TZIC2_BASE(PCELLID3_OFFSET + 0x0)
+
+
+
/*
- * Memory
- * : SROM, Onenand, Nand, SDRAM
+ * Memory : SDRAM, SROM, OneNand
*/
+/* DRAM Memory Controller */
+#define S5P_DMC_BASE(x) (S5P_PA_DMC + (x))
+
+#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */
+#define MEMCONTROL_OFFSET 0x04 /* Memory Control Register */
+#define MEMCONFIG0_OFFSET 0x08 /* Memory Chip0 Configuration Register */
+#define MEMCONFIG1_OFFSET 0x0c /* Memory Chip1 Configuration Register */
+#define DIRECTCMD_OFFSET 0x10 /* Memory Direct Command Register */
+#define PRECHCONFIG_OFFSET 0x14 /* Precharge Policy Configuration Register */
+#define PHYCONTROL0_OFFSET 0x18 /* PHY Control0 Register */
+#define PHYCONTROL1_OFFSET 0x1c /* PHY Control1 Register */
+#define PHYCONTROL2_OFFSET 0x20 /* PHY Control2 Register */
+#define PWRDNCONFIG_OFFSET 0x28 /* Dynamic Power Down Configuration Register */
+#define TIMINGAREF_OFFSET 0x30 /* AC Timing Register for SDRAM Auto Refresh */
+#define TIMINGROW_OFFSET 0x34 /* AC Timing Register for SDRAM Row */
+#define TIMINGDATA_OFFSET 0x38 /* AC Timing Register for SDRAM Data */
+#define TIMINGPOWER_OFFSET 0x3c /* AC Timing Register for Power Mode of SDRAM */
+#define PHYSTATUS0_OFFSET 0x40 /* PHY Status Register 0 */
+#define PHYSTATUS1_OFFSET 0x44 /* PHY Status Register 1 */
+#define CHIP0STATUS_OFFSET 0x48 /* Memory Chip0 Status Register */
+#define CHIP1STATUS_OFFSET 0x4c /* Memory Chip1 Status Register */
+#define AREFSTATUS_OFFSET 0x50 /* Counter status Register for Auto Refresh */
+#define MRSTATUS_OFFSET 0x54 /* Memory Mode Registers Status Register */
+#define PHYTEST0_OFFSET 0x58 /* PHY Test Register 0 */
+#define PHYTEST1_OFFSET 0x5c /* PHY Test Register 1 */
+#define QOSCONTROL0_OFFSET 0x60 /* Quality of Service Control Register 0 */
+#define QOSCONFIG0_OFFSET 0x64 /* Quality of Service Configuration Register 0 */
+#define QOSCONTROL1_OFFSET 0x68
+#define QOSCONFIG1_OFFSET 0x6c
+#define QOSCONTROL2_OFFSET 0x70
+#define QOSCONFIG2_OFFSET 0x74
+#define QOSCONTROL3_OFFSET 0x78
+#define QOSCONFIG3_OFFSET 0x7c
+#define QOSCONTROL4_OFFSET 0x80
+#define QOSCONFIG4_OFFSET 0x84
+#define QOSCONTROL5_OFFSET 0x88
+#define QOSCONFIG5_OFFSET 0x8c
+#define QOSCONTROL6_OFFSET 0x90
+#define QOSCONFIG6_OFFSET 0x94
+#define QOSCONTROL7_OFFSET 0x98
+#define QOSCONFIG7_OFFSET 0x9c
+
+#define S5P_CONCONTROL S5P_DMC_BASE(CONCONTROL_OFFSET)
+#define S5P_MEMCONTROL S5P_DMC_BASE(MEMCONTROL_OFFSET)
+#define S5P_MEMCONFIG0 S5P_DMC_BASE(MEMCONFIG0_OFFSET)
+#define S5P_MEMCONFIG1 S5P_DMC_BASE(MEMCONFIG1_OFFSET)
+#define S5P_DIRECTCMD S5P_DMC_BASE(DIRECTCMD_OFFSET)
+#define S5P_PRECHCONFIG S5P_DMC_BASE(PRECHCONFIG_OFFSET)
+#define S5P_PHYCONTROL0 S5P_DMC_BASE(PHYCONTROL0_OFFSET)
+#define S5P_PHYCONTROL1 S5P_DMC_BASE(PHYCONTROL1_OFFSET)
+#define S5P_PHYCONTROL2 S5P_DMC_BASE(PHYCONTROL2_OFFSET)
+#define S5P_PWRDNCONFIG S5P_DMC_BASE(PWRDNCONFIG_OFFSET)
+#define S5P_TIMINGAREF S5P_DMC_BASE(TIMINGAREF_OFFSET)
+#define S5P_TIMINGROW S5P_DMC_BASE(TIMINGROW_OFFSET)
+#define S5P_TIMINGDATA S5P_DMC_BASE(TIMINGDATA_OFFSET)
+#define S5P_TIMINGPOWER S5P_DMC_BASE(TIMINGPOWER_OFFSET)
+#define S5P_PHYSTATUS0 S5P_DMC_BASE(PHYSTATUS0_OFFSET)
+#define S5P_PHYSTATUS1 S5P_DMC_BASE(PHYSTATUS1_OFFSET)
+#define S5P_CHIP0STATUS S5P_DMC_BASE(CHIP0STATUS_OFFSET)
+#define S5P_CHIP1STATUS S5P_DMC_BASE(CHIP1STATUS_OFFSET)
+#define S5P_AREFSTATUS S5P_DMC_BASE(AREFSTATUS_OFFSET)
+#define S5P_MRSTATUS S5P_DMC_BASE(MRSTATUS_OFFSET)
+#define S5P_PHYTEST0 S5P_DMC_BASE(PHYTEST0_OFFSET)
+#define S5P_PHYTEST1 S5P_DMC_BASE(PHYTEST1_OFFSET)
+
+#define S5P_QOSCONTROL0 S5P_DMC_BASE(QOSCONTROL0_OFFSET)
+#define S5P_QOSCONFIG0 S5P_DMC_BASE(QOSCONFIG0_OFFSET)
+#define S5P_QOSCONTROL1 S5P_DMC_BASE(QOSCONTROL1_OFFSET)
+#define S5P_QOSCONFIG1 S5P_DMC_BASE(QOSCONFIG1_OFFSET)
+#define S5P_QOSCONTROL2 S5P_DMC_BASE(QOSCONTROL2_OFFSET)
+#define S5P_QOSCONFIG2 S5P_DMC_BASE(QOSCONFIG2_OFFSET)
+#define S5P_QOSCONTROL3 S5P_DMC_BASE(QOSCONTROL3_OFFSET)
+#define S5P_QOSCONFIG3 S5P_DMC_BASE(QOSCONFIG3_OFFSET)
+#define S5P_QOSCONTROL4 S5P_DMC_BASE(QOSCONTROL4_OFFSET)
+#define S5P_QOSCONFIG4 S5P_DMC_BASE(QOSCONFIG4_OFFSET)
+#define S5P_QOSCONTROL5 S5P_DMC_BASE(QOSCONTROL5_OFFSET)
+#define S5P_QOSCONFIG5 S5P_DMC_BASE(QOSCONFIG5_OFFSET)
+#define S5P_QOSCONTROL6 S5P_DMC_BASE(QOSCONTROL6_OFFSET)
+#define S5P_QOSCONFIG6 S5P_DMC_BASE(QOSCONFIG6_OFFSET)
+#define S5P_QOSCONTROL7 S5P_DMC_BASE(QOSCONTROL7_OFFSET)
+#define S5P_QOSCONFIG7 S5P_DMC_BASE(QOSCONFIG7_OFFSET)
+
+
+/* SROM */
+#define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x))
+
+#define SROM_BW_OFFSET 0x0
+#define SROM_BC0_OFFSET 0x04
+#define SROM_BC1_OFFSET 0x08
+#define SROM_BC2_OFFSET 0x0c
+#define SROM_BC3_OFFSET 0x10
+#define SROM_BC4_OFFSET 0x14
+#define SROM_BC5_OFFSET 0x18
+
+#define S5P_SROM_BW __REG(S5P_SROMC_BASE(SROM_BW_OFFSET))
+#define S5P_SROM_BC0 __REG(S5P_SROMC_BASE(SROM_BC0_OFFSET))
+#define S5P_SROM_BC1 S5P_SROMC_BASE(SROM_BC1_OFFSET)
+#define S5P_SROM_BC2 S5P_SROMC_BASE(SROM_BC2_OFFSET)
+#define S5P_SROM_BC3 S5P_SROMC_BASE(SROM_BC3_OFFSET)
+#define S5P_SROM_BC4 S5P_SROMC_BASE(SROM_BC4_OFFSET)
+#define S5P_SROM_BC5 S5P_SROMC_BASE(SROM_BC5_OFFSET)
+
+
+/* OneNand */
+#define S5P_ONENANDC_BASE(x) (S5P_PA_ONENANDC + (x))
+
+#define MEM_CFG_OFFSET 0x0
+#define BURST_LEN_OFFSET 0x10
+#define MEM_RESET_OFFSET 0x20
+#define INT_ERR_STAT_OFFSET 0x30
+#define INT_ERR_MASK_OFFSET 0x40
+#define INT_ERR_ACK_OFFSET 0x50
+#define ECC_ERR_STAT_1_OFFSET 0x60
+#define MANUFACT_ID_OFFSET 0x70
+#define DEVICE_ID_OFFSET 0x80
+#define DATA_BUF_SIZE_OFFSET 0x90
+#define BOOT_BUF_SIZE_OFFSET 0xa0
+#define BUF_AMOUNT_OFFSET 0xb0
+#define TECH_OFFSET 0xc0
+#define FBA_WIDTH_OFFSET 0xd0
+#define FPA_WIDTH_OFFSET 0xe0
+#define FSA_WIDTH_OFFSET 0xf0
+#define REVISION_OFFSET 0x100
+#define SYNC_MODE_OFFSET 0x130
+#define TRANS_SPARE_OFFSET 0x140
+#define PAGE_CNT_OFFSET 0x170
+#define ERR_PAGE_ADDR_OFFSET 0x180
+#define BURST_RD_LAT_OFFSET 0x190
+#define INT_PIN_ENABLE_OFFSET 0x1a0
+#define INT_MON_CYC_OFFSET 0x1b0
+#define ACC_CLOCK_OFFSET 0x1c0
+#define ERR_BLK_ADDR_OFFSET 0x1e0
+#define FLASH_VER_ID_OFFSET 0x1f0
+#define BANK_EN_OFFSET 0x220
+#define WTCHDG_RST_L_OFFSET 0x260
+#define WTCHDG_RST_H_OFFSET 0x270
+#define SYNC_WRITE_OFFSET 0x280
+#define CACHE_READ_OFFSET 0x290
+#define COLD_RST_DLY_OFFSET 0x2a0
+#define DDP_DEVICE_OFFSET 0x2b0
+#define MULTI_PLANE_OFFSET 0x2c0
+#define TRANS_MODE_OFFSET 0x2e0
+#define DEV_STAT_OFFSET 0x2f0
+#define ECC_ERR_STAT_2_OFFSET 0x300
+#define ECC_ERR_STAT_3_OFFSET 0x310
+#define ECC_ERR_STAT_4_OFFSET 0x320
+#define EFCT_BUF_CNT_OFFSET 0x330
+#define DEV_PAGE_SIZE_OFFSET 0x340
+#define SUPERLOAD_EN_OFFSET 0x350
+#define CACHE_PRG_EN_OFFSET 0x360
+#define SINGLE_PAGE_BUF_OFFSET 0x370
+#define OFFSET_ADDR_OFFSET 0x380
+#define INT_MON_STATUS_OFFSET 0x390
+
+#define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET)
+#define S5P_BURST_LEN S5P_ONENANDC_BASE(BURST_LEN_OFFSET)
+#define S5P_MEM_RESET S5P_ONENANDC_BASE(MEM_RESET_OFFSET)
+#define S5P_INT_ERR_STAT S5P_ONENANDC_BASE(INT_ERR_STAT_OFFSET)
+#define S5P_INT_ERR_MASK S5P_ONENANDC_BASE(INT_ERR_MASK_OFFSET)
+#define S5P_INT_ERR_ACK S5P_ONENANDC_BASE(INT_ERR_ACK_OFFSET)
+#define S5P_ECC_ERR_STAT_1 S5P_ONENANDC_BASE(ECC_ERR_STAT_1_OFFSET)
+#define S5P_MANUFACT_ID S5P_ONENANDC_BASE(MANUFACT_ID_OFFSET)
+#define S5P_DEVICE_ID S5P_ONENANDC_BASE(DEVICE_ID_OFFSET)
+#define S5P_DATA_BUF_SIZE S5P_ONENANDC_BASE(DATA_BUF_SIZE_OFFSET)
+#define S5P_BOOT_BUF_SIZE S5P_ONENANDC_BASE(BOOT_BUF_SIZE_OFFSET)
+#define S5P_BUF_AMOUNT S5P_ONENANDC_BASE(BUF_AMOUNT_OFFSET)
+#define S5P_TECH S5P_ONENANDC_BASE(TECH_OFFSET)
+#define S5P_FBA_WIDTH S5P_ONENANDC_BASE(FBA_WIDTH_OFFSET)
+#define S5P_FPA_WIDTH S5P_ONENANDC_BASE(FPA_WIDTH_OFFSET)
+#define S5P_FSA_WIDTH S5P_ONENANDC_BASE(FSA_WIDTH_OFFSET)
+#define S5P_REVISION S5P_ONENANDC_BASE(REVISION_OFFSET)
+#define S5P_SYNC_MODE S5P_ONENANDC_BASE(SYNC_MODE_OFFSET)
+#define S5P_TRANS_SPARE S5P_ONENANDC_BASE(TRANS_SPARE_OFFSET)
+#define S5P_PAGE_CNT S5P_ONENANDC_BASE(PAGE_CNT_OFFSET)
+#define S5P_ERR_PAGE_ADDR S5P_ONENANDC_BASE(ERR_PAGE_ADDR_OFFSET)
+#define S5P_BURST_RD_LAT S5P_ONENANDC_BASE(BURST_RD_LAT_OFFSET)
+#define S5P_INT_PIN_ENABLE S5P_ONENANDC_BASE(INT_PIN_ENABLE_OFFSET)
+#define S5P_INT_MON_CYC S5P_ONENANDC_BASE(INT_MON_CYC_OFFSET)
+#define S5P_ACC_CLOCK S5P_ONENANDC_BASE(ACC_CLOCK_OFFSET)
+#define S5P_ERR_BLK_ADDR S5P_ONENANDC_BASE(ERR_BLK_ADDR_OFFSET)
+#define S5P_FLASH_VER_ID S5P_ONENANDC_BASE(FLASH_VER_ID_OFFSET)
+#define S5P_BANK_EN S5P_ONENANDC_BASE(BANK_EN_OFFSET)
+#define S5P_WTCHDG_RST_L S5P_ONENANDC_BASE(WTCHDG_RST_L_OFFSET)
+#define S5P_WTCHDG_RST_H S5P_ONENANDC_BASE(WTCHDG_RST_H_OFFSET)
+#define S5P_SYNC_WRITE S5P_ONENANDC_BASE(SYNC_WRITE_OFFSET)
+#define S5P_CACHE_READ S5P_ONENANDC_BASE(CACHE_READ_OFFSET)
+#define S5P_COLD_RST_DLY S5P_ONENANDC_BASE(COLD_RST_DLY_OFFSET)
+#define S5P_DDP_DEVICE S5P_ONENANDC_BASE(DDP_DEVICE_OFFSET)
+#define S5P_MULTI_PLANE S5P_ONENANDC_BASE(MULTI_PLANE_OFFSET)
+#define S5P_MEM_CNT S5P_ONENANDC_BASE(MEM_CNT_OFFSET)
+#define S5P_TRANS_MODE S5P_ONENANDC_BASE(TRANS_MODE_OFFSET)
+#define S5P_DEV_START S5P_ONENANDC_BASE(DEV_START_OFFSET)
+#define S5P_ECC_ERR_STAT_2 S5P_ONENANDC_BASE(ECC_ERR_STAT_2_OFFSET)
+#define S5P_ECC_ERR_STAT_3 S5P_ONENANDC_BASE(ECC_ERR_STAT_3_OFFSET)
+#define S5P_ECC_ERR_STAT_4 S5P_ONENANDC_BASE(ECC_ERR_STAT_4_OFFSET)
+#define S5P_EFCT_BUF_CNT S5P_ONENANDC_BASE(EFCT_BUF_CNT_OFFSET)
+#define S5P_DEV_PAGE_SIZE S5P_ONENANDC_BASE(DEV_PAGE_SIZE_OFFSET)
+#define S5P_SUPERLOAD_EN S5P_ONENANDC_BASE(SUPERLOAD_EN_OFFSET)
+#define S5P_CACHE_PRG_EN S5P_ONENANDC_BASE(CACHE_PRG_EN_OFFSET)
+#define S5P_SINGLE_PAGE_BUF S5P_ONENANDC_BASE(SINGLE_PAGE_BUF_OFFSET)
+#define S5P_OFFSET_ADDR S5P_ONENANDC_BASE(OFFSET_ADDR_OFFSET)
+#define S5P_INT_MON_STATUS S5P_ONENANDC_BASE(INT_MON_STATUS_OFFSET)
+
+
+
/*
* Timer
* : PWM, Watchdog, System timer, RTC
*/
+/* PWM */
+#define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x))
+
+#define PWM_TCFG0_OFFSET 0x0
+#define PWM_TCFG1_OFFSET 0x04
+#define PWM_TCON_OFFSET 0x08
+#define PWM_TCNTB0_OFFSET 0x0c
+#define PWM_TCMPB0_OFFSET 0x10
+#define PWM_TCNTO0_OFFSET 0x14
+#define PWM_TCNTB1_OFFSET 0x18
+#define PWM_TCMPB1_OFFSET 0x1c
+#define PWM_TCNTO1_OFFSET 0x20
+#define PWM_TCNTB2_OFFSET 0x24
+#define PWM_TCMPB2_OFFSET 0x28
+#define PWM_TCNTO2_OFFSET 0x2c
+#define PWM_TCNTB3_OFFSET 0x30
+#define PWM_TCNTO3_OFFSET 0x38
+#define PWM_TCNTB4_OFFSET 0x3c
+#define PWM_TCNTO4_OFFSET 0x40
+#define PWM_TINT_CSTAT_OFFSET 0x44
+
+#define S5P_PWM_TCFG0 S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET)
+#define S5P_PWM_TCFG1 S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET)
+#define S5P_PWM_TCON S5P_PWMTIMER_BASE(PWM_TCON_OFFSET)
+#define S5P_PWM_TCNTB0 S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET)
+#define S5P_PWM_TCMPB0 S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET)
+#define S5P_PWM_TCNTO0 S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET)
+#define S5P_PWM_TCNTB1 S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET)
+#define S5P_PWM_TCMPB1 S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET)
+#define S5P_PWM_TCNTO1 S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET)
+#define S5P_PWM_TCNTB2 S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET)
+#define S5P_PWM_TCMPB2 S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET)
+#define S5P_PWM_TCNTO2 S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET)
+#define S5P_PWM_TCNTB3 S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET)
+#define S5P_PWM_TCNTO3 S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET)
+#define S5P_PWM_TCNTB4 S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET)
+#define S5P_PWM_TCNTO4 S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET)
+#define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET)
+
+
+/* System Timer */
+#define S5P_SYSTIMER_BASE(x) (S5P_PA_SYSTEM + (x))
+
+#define SYS_TCFG_OFFSET 0x0
+#define SYS_TCON_OFFSET 0x04
+#define SYS_TCNTB_OFFSET 0x08
+#define SYS_TCNTO_OFFSET 0x0c
+#define SYS_ICNTB_OFFSET 0x10
+#define SYS_ICNTO_OFFSET 0x14
+#define SYS_INT_CSTAT_OFFSET 0x18
+
+#define S5P_SYS_TCFG S5P_SYSTIMER_BASE(SYS_TCFG_OFFSET)
+#define S5P_SYS_TCON S5P_SYSTIMER_BASE(SYS_TCON_OFFSET)
+#define S5P_SYS_TCNTB S5P_SYSTIMER_BASE(SYS_TCNTB_OFFSET)
+#define S5P_SYS_TCNTO S5P_SYSTIMER_BASE(SYS_TCNTO_OFFSET)
+#define S5P_SYS_ICNTB S5P_SYSTIMER_BASE(SYS_ICNTB_OFFSET)
+#define S5P_SYS_ICNTO S5P_SYSTIMER_BASE(SYS_ICNTO_OFFSET)
+#define S5P_SYS_INT_CSTAT S5P_SYSTIMER_BASE(SYS_INT_CSTAT_OFFSET)
+
+
+/* Watchdog */
+#define S5P_WATCHDOG_BASE(x) (S5P_PA_WATCHDOG + (x))
+
+#define WTCON_OFFSET 0x0
+#define WTDAT_OFFSET 0x4
+#define WTCNT_OFFSET 0x8
+#define WTCLRINT_OFFSET 0xc
+
+#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET)
+#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET)
+#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET)
+#define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET)
+
+
+/* RTC */
+#define S5P_RTC_BASE(x) (S5P_PA_RTC + (x))
+
+#define INTP_OFFSET 0x30
+#define RTCCON_OFFSET 0x40
+#define TICCNT_OFFSET 0x44
+#define RTCALM_OFFSET 0x50
+
+#define ALMSEC_OFFSET 0x54
+#define ALMMIN_OFFSET 0x58
+#define ALMHOUR_OFFSET 0x5c
+#define ALMDATE_OFFSET 0x60
+#define ALMMON_OFFSET 0x64
+#define ALMYEAR_OFFSET 0x68
+
+#define BCDSEC_OFFSET 0x70
+#define BCDMIN_OFFSET 0x74
+#define BCDHOUR_OFFSET 0x78
+#define BCDDATE_OFFSET 0x7c
+#define BCDDAY_OFFSET 0x80
+#define BCDMON_OFFSET 0x84
+#define BCDYEAR_OFFSET 0x88
+
+#define CURTICCNT 0x90
+
+
+
+
+#define S5P_INTP S5P_RTC_BASE(INTP_OFFSET)
+#define S5P_RTCCON S5P_RTC_BASE(RTCCON_OFFSET)
+#define S5P_TICCNT S5P_RTC_BASE(TICCNT_OFFSET)
+#define S5P_RTCALM S5P_RTC_BASE(RTCALM_OFFSET)
+
+#define S5P_ALMSEC S5P_RTC_BASE(ALMSEC_OFFSET)
+#define S5P_ALMMIN S5P_RTC_BASE(ALMMIN_FFSET)
+#define S5P_ALMHOUR S5P_RTC_BASE(ALMHOUR_OFFSET)
+#define S5P_ALMDATE S5P_RTC_BASE(ALMDATE_OFFSET)
+#define S5P_ALMMON S5P_RTC_BASE(ALMMON_OFFSET)
+#define S5P_ALMYEAR S5P_RTC_BASE(ALMYEAR_OFFSET)
+
+#define S5P_BCDSEC S5P_RTC_BASE(BCDSEC_OFFSET)
+#define S5P_BCDMIN S5P_RTC_BASE(BCDMIN_OFFSET)
+#define S5P_BCDHOUR S5P_RTC_BASE(BCDHOUR_OFFSET)
+#define S5P_BCDDATE S5P_RTC_BASE(BCDDATE_OFFSET)
+#define S5P_BCDDAY S5P_RTC_BASE(BCDDAY_OFFSET)
+#define S5P_BCDMON S5P_RTC_BASE(BCDMON_OFFSET)
+#define S5P_BCDYEAR S5P_RTC_BASE(BCDYEAR_OFFSET)
+
+#define S5P_CURTICCNT S5P_RTC_BASE(CURTICCNT_OFFSET)
/*
#define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */
-#endif /*__S5PC100_H__*/
+//#endif /*__S5PC100_H__*/
+
projects / kernel / u-boot.git / commitdiff