dt-bindings: clk: gxbb-clkc: expose all clock ids

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every gxbb-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 6751cda..798ffb9 100644 (file)
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -112,82 +112,6 @@
 #define HHI_BT656_CLK_CNTL             0x3D4 /* 0xf5 offset in data sheet */
 #define HHI_SAR_CLK_CNTL               0x3D8 /* 0xf6 offset in data sheet */
 
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
-#define CLKID_MPEG_SEL           10
-#define CLKID_MPEG_DIV           11
-#define CLKID_SAR_ADC_DIV        99
-#define CLKID_MALI_0_DIV         101
-#define CLKID_MALI_1_DIV         104
-#define CLKID_CTS_AMCLK_SEL      108
-#define CLKID_CTS_AMCLK_DIV      109
-#define CLKID_CTS_MCLK_I958_SEL          111
-#define CLKID_CTS_MCLK_I958_DIV          112
-#define CLKID_32K_CLK_SEL        115
-#define CLKID_32K_CLK_DIV        116
-#define CLKID_SD_EMMC_A_CLK0_SEL  117
-#define CLKID_SD_EMMC_A_CLK0_DIV  118
-#define CLKID_SD_EMMC_B_CLK0_SEL  120
-#define CLKID_SD_EMMC_B_CLK0_DIV  121
-#define CLKID_SD_EMMC_C_CLK0_SEL  123
-#define CLKID_SD_EMMC_C_CLK0_DIV  124
-#define CLKID_VPU_0_DIV                  127
-#define CLKID_VPU_1_DIV                  130
-#define CLKID_VAPB_0_DIV         134
-#define CLKID_VAPB_1_DIV         137
-#define CLKID_HDMI_PLL_PRE_MULT          141
-#define CLKID_MPLL0_DIV                  142
-#define CLKID_MPLL1_DIV                  143
-#define CLKID_MPLL2_DIV                  144
-#define CLKID_MPLL_PREDIV        145
-#define CLKID_FCLK_DIV2_DIV      146
-#define CLKID_FCLK_DIV3_DIV      147
-#define CLKID_FCLK_DIV4_DIV      148
-#define CLKID_FCLK_DIV5_DIV      149
-#define CLKID_FCLK_DIV7_DIV      150
-#define CLKID_VDEC_1_SEL         151
-#define CLKID_VDEC_1_DIV         152
-#define CLKID_VDEC_HEVC_SEL      154
-#define CLKID_VDEC_HEVC_DIV      155
-#define CLKID_GEN_CLK_SEL        157
-#define CLKID_GEN_CLK_DIV        158
-#define CLKID_FIXED_PLL_DCO      160
-#define CLKID_HDMI_PLL_DCO       161
-#define CLKID_HDMI_PLL_OD        162
-#define CLKID_HDMI_PLL_OD2       163
-#define CLKID_SYS_PLL_DCO        164
-#define CLKID_GP0_PLL_DCO        165
-#define CLKID_VID_PLL_SEL        167
-#define CLKID_VID_PLL_DIV        168
-#define CLKID_VCLK_SEL           169
-#define CLKID_VCLK2_SEL                  170
-#define CLKID_VCLK_INPUT         171
-#define CLKID_VCLK2_INPUT        172
-#define CLKID_VCLK_DIV           173
-#define CLKID_VCLK2_DIV                  174
-#define CLKID_VCLK_DIV2_EN       177
-#define CLKID_VCLK_DIV4_EN       178
-#define CLKID_VCLK_DIV6_EN       179
-#define CLKID_VCLK_DIV12_EN      180
-#define CLKID_VCLK2_DIV2_EN      181
-#define CLKID_VCLK2_DIV4_EN      182
-#define CLKID_VCLK2_DIV6_EN      183
-#define CLKID_VCLK2_DIV12_EN     184
-#define CLKID_CTS_ENCI_SEL       195
-#define CLKID_CTS_ENCP_SEL       196
-#define CLKID_CTS_VDAC_SEL       197
-#define CLKID_HDMI_TX_SEL        198
-#define CLKID_HDMI_SEL           203
-#define CLKID_HDMI_DIV           204
-
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
 

diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 4073eb7..c0ce5e9 100644 (file)
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -15,6 +15,8 @@
 #define CLKID_FCLK_DIV5                7
 #define CLKID_FCLK_DIV7                8
 #define CLKID_GP0_PLL          9
+#define CLKID_MPEG_SEL         10
+#define CLKID_MPEG_DIV         11
 #define CLKID_CLK81            12
 #define CLKID_MPLL0            13
 #define CLKID_MPLL1            14
@@ -102,35 +104,92 @@
 #define CLKID_SD_EMMC_C                96
 #define CLKID_SAR_ADC_CLK      97
 #define CLKID_SAR_ADC_SEL      98
+#define CLKID_SAR_ADC_DIV      99
 #define CLKID_MALI_0_SEL       100
+#define CLKID_MALI_0_DIV       101
 #define CLKID_MALI_0           102
 #define CLKID_MALI_1_SEL       103
+#define CLKID_MALI_1_DIV       104
 #define CLKID_MALI_1           105
 #define CLKID_MALI             106
 #define CLKID_CTS_AMCLK                107
+#define CLKID_CTS_AMCLK_SEL    108
+#define CLKID_CTS_AMCLK_DIV    109
 #define CLKID_CTS_MCLK_I958    110
+#define CLKID_CTS_MCLK_I958_SEL        111
+#define CLKID_CTS_MCLK_I958_DIV 112
 #define CLKID_CTS_I958         113
 #define CLKID_32K_CLK          114
+#define CLKID_32K_CLK_SEL      115
+#define CLKID_32K_CLK_DIV      116
+#define CLKID_SD_EMMC_A_CLK0_SEL 117
+#define CLKID_SD_EMMC_A_CLK0_DIV 118
 #define CLKID_SD_EMMC_A_CLK0   119
+#define CLKID_SD_EMMC_B_CLK0_SEL 120
+#define CLKID_SD_EMMC_B_CLK0_DIV 121
 #define CLKID_SD_EMMC_B_CLK0   122
+#define CLKID_SD_EMMC_C_CLK0_SEL 123
+#define CLKID_SD_EMMC_C_CLK0_DIV 124
 #define CLKID_SD_EMMC_C_CLK0   125
 #define CLKID_VPU_0_SEL                126
+#define CLKID_VPU_0_DIV                127
 #define CLKID_VPU_0            128
 #define CLKID_VPU_1_SEL                129
+#define CLKID_VPU_1_DIV                130
 #define CLKID_VPU_1            131
 #define CLKID_VPU              132
 #define CLKID_VAPB_0_SEL       133
+#define CLKID_VAPB_0_DIV       134
 #define CLKID_VAPB_0           135
 #define CLKID_VAPB_1_SEL       136
+#define CLKID_VAPB_1_DIV       137
 #define CLKID_VAPB_1           138
 #define CLKID_VAPB_SEL         139
 #define CLKID_VAPB             140
+#define CLKID_HDMI_PLL_PRE_MULT        141
+#define CLKID_MPLL0_DIV                142
+#define CLKID_MPLL1_DIV                143
+#define CLKID_MPLL2_DIV                144
+#define CLKID_MPLL_PREDIV      145
+#define CLKID_FCLK_DIV2_DIV    146
+#define CLKID_FCLK_DIV3_DIV    147
+#define CLKID_FCLK_DIV4_DIV    148
+#define CLKID_FCLK_DIV5_DIV    149
+#define CLKID_FCLK_DIV7_DIV    150
+#define CLKID_VDEC_1_SEL       151
+#define CLKID_VDEC_1_DIV       152
 #define CLKID_VDEC_1           153
+#define CLKID_VDEC_HEVC_SEL    154
+#define CLKID_VDEC_HEVC_DIV    155
 #define CLKID_VDEC_HEVC                156
+#define CLKID_GEN_CLK_SEL      157
+#define CLKID_GEN_CLK_DIV      158
 #define CLKID_GEN_CLK          159
+#define CLKID_FIXED_PLL_DCO    160
+#define CLKID_HDMI_PLL_DCO     161
+#define CLKID_HDMI_PLL_OD      162
+#define CLKID_HDMI_PLL_OD2     163
+#define CLKID_SYS_PLL_DCO      164
+#define CLKID_GP0_PLL_DCO      165
 #define CLKID_VID_PLL          166
+#define CLKID_VID_PLL_SEL      167
+#define CLKID_VID_PLL_DIV      168
+#define CLKID_VCLK_SEL         169
+#define CLKID_VCLK2_SEL                170
+#define CLKID_VCLK_INPUT       171
+#define CLKID_VCLK2_INPUT      172
+#define CLKID_VCLK_DIV         173
+#define CLKID_VCLK2_DIV                174
 #define CLKID_VCLK             175
 #define CLKID_VCLK2            176
+#define CLKID_VCLK_DIV2_EN     177
+#define CLKID_VCLK_DIV4_EN     178
+#define CLKID_VCLK_DIV6_EN     179
+#define CLKID_VCLK_DIV12_EN    180
+#define CLKID_VCLK2_DIV2_EN    181
+#define CLKID_VCLK2_DIV4_EN    182
+#define CLKID_VCLK2_DIV6_EN    183
+#define CLKID_VCLK2_DIV12_EN   184
 #define CLKID_VCLK_DIV1                185
 #define CLKID_VCLK_DIV2                186
 #define CLKID_VCLK_DIV4                187
@@ -141,10 +200,16 @@
 #define CLKID_VCLK2_DIV4       192
 #define CLKID_VCLK2_DIV6       193
 #define CLKID_VCLK2_DIV12      194
+#define CLKID_CTS_ENCI_SEL     195
+#define CLKID_CTS_ENCP_SEL     196
+#define CLKID_CTS_VDAC_SEL     197
+#define CLKID_HDMI_TX_SEL      198
 #define CLKID_CTS_ENCI         199
 #define CLKID_CTS_ENCP         200
 #define CLKID_CTS_VDAC         201
 #define CLKID_HDMI_TX          202
+#define CLKID_HDMI_SEL         203
+#define CLKID_HDMI_DIV         204
 #define CLKID_HDMI             205
 #define CLKID_ACODEC           206