kSFPImmediate, ///< Single-floating-point immediate operand.
kDFPImmediate, ///< Double-Floating-point immediate operand.
};
- MCAOperandType Kind = kInvalid;
+ MCAOperandType Kind;
union {
unsigned RegVal;
unsigned Index;
public:
- MCAOperand() : FPImmVal(0) {}
+
+ MCAOperand() : Kind(kInvalid), FPImmVal(), Index() {}
bool isValid() const { return Kind != kInvalid; }
bool isReg() const { return Kind == kRegister; }
computeMaxLatency(*ID, MCDesc, SCDesc, STI);
if (Error Err = verifyOperands(MCDesc, MCI))
- return std::move(Err);
+ return Err;
populateWrites(*ID, MCI, SchedClassID);
populateReads(*ID, MCI, SchedClassID);
// Sanity check on the instruction descriptor.
if (Error Err = verifyInstrDesc(*ID, MCI))
- return std::move(Err);
+ return Err;
// Now add the new descriptor.
bool IsVariadic = MCDesc.isVariadic();
// Early exit if there are no writes.
if (D.Writes.empty())
- return std::move(NewIS);
+ return NewIS;
// Track register writes that implicitly clear the upper portion of the
// underlying super-registers using an APInt.
++WriteIndex;
}
- return std::move(NewIS);
+ return NewIS;
}
} // namespace mca
} // namespace llvm