drm/amdgpu: add judgement for suspend/resume sequence
authorLikun Gao <Likun.Gao@amd.com>
Tue, 15 Dec 2020 16:32:20 +0000 (11:32 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Dec 2020 16:32:46 +0000 (11:32 -0500)
S0ix only makes sense on APUs since they are part of the platform, so
only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag
to deal with the related situation.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 6e2953233231fa4658ae8a02b112632dc67c1f69..b24de64f4490961b7ec964f8d6d671dc43cdac01 100644 (file)
@@ -1311,11 +1311,11 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
 
 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
                struct amdgpu_dm_backlight_caps *caps);
-bool amdgpu_acpi_is_s0ix_supported(void);
+bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
-static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; }
+static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
 #endif
 
 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
index 4f4fda53c08a7127871af74bd7237c414837dbeb..8155c54392c885a96f93cb7bf789a266fe08bb38 100644 (file)
@@ -901,10 +901,12 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev)
  *
  * returns true if supported, false if not.
  */
-bool amdgpu_acpi_is_s0ix_supported(void)
+bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)
 {
-       if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
-               return true;
+       if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
+               if (adev->flags & AMD_IS_APU)
+                       return true;
+       }
 
        return false;
 }
index 79dd85f71fabc6d0604e5e5d7808a99f1372d120..0ec7c28c4d5a3b6d92911990462a2e2419182561 100644 (file)
@@ -2650,7 +2650,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
 {
        int i, r;
 
-       if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) {
+       if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
                amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
                amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
        }
@@ -3710,7 +3710,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
        amdgpu_fence_driver_suspend(adev);
 
-       if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev))
+       if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
                r = amdgpu_device_ip_suspend_phase2(adev);
        else
                amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
@@ -3744,7 +3744,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
        if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
                return 0;
 
-       if (amdgpu_acpi_is_s0ix_supported())
+       if (amdgpu_acpi_is_s0ix_supported(adev))
                amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
 
        /* post card */