[libc] Implement memory fences on NVPTX

Memory fences are not handled by the NVPTX backend. We need to replace
them with a memory barrier intrinsic function. This doesn't include the
ordering, but should perform the necessary functionality, albeit slower.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D146725

diff --git a/libc/src/__support/CPP/atomic.h b/libc/src/__support/CPP/atomic.h
index b0e90e3..5514062 100644 (file)
--- a/libc/src/__support/CPP/atomic.h
+++ b/libc/src/__support/CPP/atomic.h
@@ -10,6 +10,7 @@
 #define LLVM_LIBC_SRC_SUPPORT_CPP_ATOMIC_H
 
 #include "src/__support/macros/attributes.h"
+#include "src/__support/macros/properties/architectures.h"
 
 #include "type_traits.h"
 
@@ -96,7 +97,14 @@ public:
 
 // Issue a thread fence with the given memory ordering.
 LIBC_INLINE void atomic_thread_fence(MemoryOrder mem_ord) {
+// The NVPTX backend currently does not support atomic thread fences so we use a
+// full system fence instead.
+#ifdef LIBC_TARGET_ARCH_IS_NVPTX
+  (void)mem_ord;
+  __nvvm_membar_sys();
+#else
   __atomic_thread_fence(int(mem_ord));
+#endif
 }
 
 } // namespace cpp