bool parseStandaloneMBB(MachineBasicBlock *&MBB);
bool parseStandaloneNamedRegister(unsigned &Reg);
bool parseStandaloneVirtualRegister(VRegInfo *&Info);
+ bool parseStandaloneRegister(unsigned &Reg);
bool parseStandaloneStackObject(int &FI);
bool parseStandaloneMDNode(MDNode *&Node);
return false;
}
+bool MIParser::parseStandaloneRegister(unsigned &Reg) {
+ lex();
+ if (Token.isNot(MIToken::NamedRegister) &&
+ Token.isNot(MIToken::VirtualRegister))
+ return error("expected either a named or virtual register");
+
+ VRegInfo *Info;
+ if (parseRegister(Reg, Info))
+ return true;
+
+ lex();
+ if (Token.isNot(MIToken::Eof))
+ return error("expected end of string after the register reference");
+ return false;
+}
+
bool MIParser::parseStandaloneStackObject(int &FI) {
lex();
if (Token.isNot(MIToken::StackObject))
return MIParser(PFS, Error, Src).parseStandaloneMBB(MBB);
}
+bool llvm::parseRegisterReference(PerFunctionMIParsingState &PFS,
+ unsigned &Reg, StringRef Src,
+ SMDiagnostic &Error) {
+ return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
+}
+
bool llvm::parseNamedRegisterReference(PerFunctionMIParsingState &PFS,
unsigned &Reg, StringRef Src,
SMDiagnostic &Error) {
MachineBasicBlock *&MBB, StringRef Src,
SMDiagnostic &Error);
+bool parseRegisterReference(PerFunctionMIParsingState &PFS,
+ unsigned &Reg, StringRef Src,
+ SMDiagnostic &Error);
+
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
StringRef Src, SMDiagnostic &Error);
if (Info.Kind != VRegInfo::NORMAL)
return error(VReg.Class.SourceRange.Start,
Twine("preferred register can only be set for normal vregs"));
- if (parseNamedRegisterReference(PFS, Info.PreferredReg,
- VReg.PreferredRegister.Value, Error))
+
+ if (parseRegisterReference(PFS, Info.PreferredReg,
+ VReg.PreferredRegister.Value, Error))
return error(Error, VReg.PreferredRegister.SourceRange);
}
}
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s
--- |
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
- # CHECK: [[@LINE+1]]:48: expected a named register
+ # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
+ # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
- { id: 1, class: gr32, preferred-register: '%0' }
- { id: 2, class: gr32, preferred-register: '%edi' }
body: |