drm/amd/display: treat memory as a single-channel for asymmetric memory v2

Previous change had been reverted since it caused hang.
Remake change to avoid defect.

[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.

[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.

Fixes: b8720ed0b87d32 ("drm/amd/display: System black screen hangs on driver load")
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 73e8878..a06e868 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -769,6 +769,43 @@ static struct wm_table ddr4_wm_table_rn = {
        }
 };
 
+static struct wm_table ddr4_1R_wm_table_rn = {
+       .entries = {
+               {
+                       .wm_inst = WM_A,
+                       .wm_type = WM_TYPE_PSTATE_CHG,
+                       .pstate_latency_us = 11.72,
+                       .sr_exit_time_us = 13.90,
+                       .sr_enter_plus_exit_time_us = 14.80,
+                       .valid = true,
+               },
+               {
+                       .wm_inst = WM_B,
+                       .wm_type = WM_TYPE_PSTATE_CHG,
+                       .pstate_latency_us = 11.72,
+                       .sr_exit_time_us = 13.90,
+                       .sr_enter_plus_exit_time_us = 14.80,
+                       .valid = true,
+               },
+               {
+                       .wm_inst = WM_C,
+                       .wm_type = WM_TYPE_PSTATE_CHG,
+                       .pstate_latency_us = 11.72,
+                       .sr_exit_time_us = 13.90,
+                       .sr_enter_plus_exit_time_us = 14.80,
+                       .valid = true,
+               },
+               {
+                       .wm_inst = WM_D,
+                       .wm_type = WM_TYPE_PSTATE_CHG,
+                       .pstate_latency_us = 11.72,
+                       .sr_exit_time_us = 13.90,
+                       .sr_enter_plus_exit_time_us = 14.80,
+                       .valid = true,
+               },
+       }
+};
+
 static struct wm_table lpddr4_wm_table_rn = {
        .entries = {
                {
@@ -953,8 +990,12 @@ void rn_clk_mgr_construct(
                } else {
                        if (is_green_sardine)
                                rn_bw_params.wm_table = ddr4_wm_table_gs;
-                       else
-                               rn_bw_params.wm_table = ddr4_wm_table_rn;
+                       else {
+                               if (ctx->dc->config.is_single_rank_dimm)
+                                       rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
+                               else
+                                       rn_bw_params.wm_table = ddr4_wm_table_rn;
+                       }
                }
                /* Saved clocks configured at boot for debug purposes */
                rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
@@ -972,6 +1013,9 @@ void rn_clk_mgr_construct(
                if (status == PP_SMU_RESULT_OK &&
                    ctx->dc_bios && ctx->dc_bios->integrated_info) {
                        rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
+                       /* treat memory config as single channel if memory is asymmetrics. */
+                       if (ctx->dc->config.is_asymmetric_memory)
+                               clk_mgr->base.bw_params->num_channels = 1;
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 82a324a..870cd7c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -308,6 +308,8 @@ struct dc_config {
 #endif
        uint64_t vblank_alignment_dto_params;
        uint8_t  vblank_alignment_max_frame_time_diff;
+       bool is_asymmetric_memory;
+       bool is_single_rank_dimm;
 };
 
 enum visual_confirm {