M: Luan Yuan <luan.yuan@amlogic.com>
F: arch/arm/boot/dts/amlogic/partition_mbox_p241_P.dtsi
+AMLOGIC TL1 SOUND CARD
+M: Xing Wang <xing.wang@amlogic.com
+F: include/dt-bindings/clock/amlogic,tl1-audio-clk.h
+F: sound/soc/amlogic/auge/*
+
+AMLOGIC TL1 AUDIO EXTERANL INPUT/OUTPUT DRIVERS
+M: Xing Wang <xing.wang@amlogic.com
+F: sound/soc/amlogic/auge/extn.c
+F: sound/soc/amlogic/auge/frhdmirx_hw.c
+F: sound/soc/amlogic/auge/frhdmirx_hw.h
+F: sound/soc/amlogic/auge/*
+
AMLOGIC LCD DRIVERS
M: Evoke Zhang <evoke.zhang@amlogic.com>
F: arch\arm\boot\dts\amlogic\mesontl1_pxp-panel.dtsi
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/clock/amlogic,tl1-clkc.h>
+#include <dt-bindings/clock/amlogic,tl1-audio-clk.h>
#include "mesong12a-bifrost.dtsi"
/ {
};
};/* end of hiubus*/
+ audiobus: audiobus@0xff600000 {
+ compatible = "amlogic, audio-controller", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xff600000 0x10000>;
+ ranges = <0x0 0xff600000 0x10000>;
+
+ clkaudio:audio_clocks {
+ compatible = "amlogic, tl1-audio-clocks";
+ #clock-cells = <1>;
+ reg = <0x0 0xb0>;
+ };
+
+ ddr_manager {
+ compatible = "amlogic, tl1-audio-ddr-manager";
+ interrupts = <
+ GIC_SPI 148 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 149 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 150 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 48 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 152 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 153 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 154 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 49 IRQ_TYPE_EDGE_RISING
+ >;
+ interrupt-names =
+ "toddr_a", "toddr_b", "toddr_c",
+ "toddr_d",
+ "frddr_a", "frddr_b", "frddr_c",
+ "frddr_d";
+ };
+ };/* end of audiobus*/
+
+ /* Sound iomap */
+ aml_snd_iomap {
+ compatible = "amlogic, snd-iomap";
+ status = "okay";
+ #address-cells=<1>;
+ #size-cells=<1>;
+ ranges;
+ pdm_bus {
+ reg = <0xFF601000 0x400>;
+ };
+ audiobus_base {
+ reg = <0xFF600000 0x1000>;
+ };
+ audiolocker_base {
+ reg = <0xFF601400 0x400>;
+ };
+ eqdrc_base {
+ reg = <0xFF602000 0x2000>;
+ };
+ reset_base {
+ reg = <0xFFD01000 0x1000>;
+ };
+ vad_base {
+ reg = <0xFF601800 0x800>;
+ };
+ };
+
cbus: cbus@ffd00000 {
compatible = "simple-bus";
reg = <0xffd00000 0x27000>;
status = "okay";
fr_auto_policy = <0>;
};
+
+ /* Audio Related start */
+ pdm_codec:dummy {
+ #sound-dai-cells = <0>;
+ compatible = "amlogic, pdm_dummy_codec";
+ status = "okay";
+ };
+
+ dummy_codec:dummy {
+ #sound-dai-cells = <0>;
+ compatible = "amlogic, aml_dummy_codec";
+ status = "okay";
+ };
+
+ auge_sound {
+ compatible = "amlogic, tl1-sound-card";
+ aml-audio-card,name = "AML-AUGESOUND";
+
+ aml-audio-card,dai-link@0 {
+ format = "dsp_a";
+ mclk-fs = <512>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdma>;
+ frame-master = <&tdma>;
+ /* slave mode */
+ /*
+ * bitclock-master = <&tdmacodec>;
+ * frame-master = <&tdmacodec>;
+ */
+ /* suffix-name, sync with android audio hal used for */
+ suffix-name = "alsaPORT-pcm";
+ tdmacpu: cpu {
+ sound-dai = <&tdma>;
+ dai-tdm-slot-tx-mask =
+ <1 1 1 1 1 1 1 1>;
+ dai-tdm-slot-rx-mask =
+ <1 1 1 1 1 1 1 1>;
+ dai-tdm-slot-num = <8>;
+ dai-tdm-slot-width = <32>;
+ system-clock-frequency = <24576000>;
+ };
+ tdmacodec: codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@1 {
+ format = "i2s";
+ mclk-fs = <256>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdmb>;
+ frame-master = <&tdmb>;
+ /* slave mode */
+ //bitclock-master = <&tdmbcodec>;
+ //frame-master = <&tdmbcodec>;
+ /* suffix-name, sync with android audio hal used for */
+ suffix-name = "alsaPORT-i2s";
+ cpu {
+ sound-dai = <&tdmb>;
+ dai-tdm-slot-tx-mask = <1 1>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ dai-tdm-slot-num = <2>;
+ /*
+ * dai-tdm-slot-tx-mask =
+ * <1 1 1 1 1 1 1 1>;
+ * dai-tdm-slot-rx-mask =
+ * <1 1 1 1 1 1 1 1>;
+ * dai-tdm-slot-num = <8>;
+ */
+ dai-tdm-slot-width = <32>;
+ system-clock-frequency = <12288000>;
+ };
+ tdmbcodec: codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@2 {
+ format = "i2s";
+ mclk-fs = <256>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdmc>;
+ frame-master = <&tdmc>;
+ /* slave mode */
+ //bitclock-master = <&tdmccodec>;
+ //frame-master = <&tdmccodec>;
+ /* suffix-name, sync with android audio hal used for */
+ //suffix-name = "alsaPORT-tdm";
+ cpu {
+ sound-dai = <&tdmc>;
+ dai-tdm-slot-tx-mask = <1 1>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ system-clock-frequency = <12288000>;
+ };
+ tdmccodec: codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@3 {
+ mclk-fs = <64>;
+ /* suffix-name, sync with android audio hal used for */
+ suffix-name = "alsaPORT-pdm";
+ cpu {
+ sound-dai = <&pdm>;
+ };
+ codec {
+ sound-dai = <&pdm_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@4 {
+ mclk-fs = <128>;
+ /* suffix-name, sync with android audio hal used for */
+ suffix-name = "alsaPORT-spdif";
+ cpu {
+ sound-dai = <&spdif_a>;
+ system-clock-frequency = <6144000>;
+ };
+ codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@5 {
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&spdif_b>;
+ system-clock-frequency = <6144000>;
+ };
+ codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@6 {
+ mclk-fs = <256>;
+ cpu {
+ sound-dai = <&extn>;
+ system-clock-frequency = <12288000>;
+ };
+ codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ };
+ /* Audio Related end */
+
}; /* end of / */
+&audiobus {
+ tdma:tdm {
+ compatible = "amlogic, tl1-snd-tdma";
+ #sound-dai-cells = <0>;
+
+ dai-tdm-lane-slot-mask-in = <1 0>;
+ dai-tdm-lane-slot-mask-out = <1 0>;
+ dai-tdm-clk-sel = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_A
+ &clkc CLKID_MPLL0>;
+ clock-names = "mclk", "clk_srcpll";
+
+ pinctrl-names = "tdm_pins";
+ pinctrl-0 = <&tdma_mclk &tdmout_a &tdmin_a>;
+
+ status = "okay";
+ };
+
+ tdmb:tdm {
+ compatible = "amlogic, tl1-snd-tdmb";
+ #sound-dai-cells = <0>;
+
+ dai-tdm-lane-slot-mask-in = <1 0 0 0>;
+ dai-tdm-lane-slot-mask-out = <1 0 0 0>;
+ dai-tdm-clk-sel = <1>;
+
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_B
+ &clkc CLKID_MPLL1>;
+ clock-names = "mclk", "clk_srcpll";
+
+ status = "okay";
+ };
+
+ tdmc:tdm {
+ compatible = "amlogic, tl1-snd-tdmc";
+ #sound-dai-cells = <0>;
+
+ dai-tdm-lane-slot-mask-in = <1 0 0 0>;
+ dai-tdm-lane-slot-mask-out = <1 0 0 0>;
+ dai-tdm-clk-sel = <2>;
+
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_C
+ &clkc CLKID_MPLL2>;
+ clock-names = "mclk", "clk_srcpll";
+
+ pinctrl-names = "tdm_pins";
+ pinctrl-0 = <&tdmout_c &tdmin_c>;
+
+ status = "okay";
+ };
+
+ spdif_a:spdif {
+ compatible = "amlogic, tl1-snd-spdif-a";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkc CLKID_MPLL0
+ &clkc CLKID_FCLK_DIV4
+ &clkaudio CLKID_AUDIO_SPDIFIN
+ &clkaudio CLKID_AUDIO_SPDIFOUT
+ &clkaudio CLKID_AUDIO_SPDIFIN_CTRL
+ &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>;
+ clock-names = "sysclk", "fixed_clk", "gate_spdifin",
+ "gate_spdifout", "clk_spdifin", "clk_spdifout";
+
+ interrupts =
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "irq_spdifin";
+
+ pinctrl-names = "spdif_pins";
+ pinctrl-0 = <&spdifout_a &spdifin_a>;
+
+ status = "okay";
+ };
+
+ spdif_b:spdif {
+ compatible = "amlogic, tl1-snd-spdif-b";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
+ &clkaudio CLKID_AUDIO_SPDIFOUTB
+ &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>;
+ clock-names = "sysclk",
+ "gate_spdifout", "clk_spdifout";
+
+ status = "okay";
+ };
+
+ pdm:pdm {
+ compatible = "amlogic, tl1-snd-pdm";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_PDM
+ &clkc CLKID_FCLK_DIV3
+ &clkc CLKID_MPLL3
+ &clkaudio CLKID_AUDIO_PDMIN0
+ &clkaudio CLKID_AUDIO_PDMIN1>;
+ clock-names = "gate",
+ "sysclk_srcpll",
+ "dclk_srcpll",
+ "pdm_dclk",
+ "pdm_sysclk";
+
+ pinctrl-names = "pdm_pins";
+ pinctrl-0 = <&pdmin>;
+
+ /* mode 0~4, defalut:1 */
+ filter_mode = <1>;
+
+ status = "okay";
+ };
+
+ extn:extn {
+ compatible = "amlogic, snd-extn";
+ #sound-dai-cells = <0>;
+
+ interrupts =
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "irq_frhdmirx";
+
+ status = "okay";
+ };
+
+}; /* end of audiobus */
+
+&pinctrl_periphs {
+ /* audio pin mux */
+
+ tdma_mclk: tdma_mclk {
+ mux { /* GPIOZ_0 */
+ groups = "mclk0_z";
+ function = "mclk0";
+ };
+ };
+
+ tdmout_a: tdmout_a {
+ mux { /* GPIOZ_1, GPIOZ_2, GPIOZ_3, GPIOZ_5, GPIOZ_6 */
+ groups = "tdma_sclk_z",
+ "tdma_fs_z",
+ "tdma_dout0_z",
+ "tdma_dout2_z",
+ "tdma_dout3_z";
+ function = "tdma_out";
+ };
+ };
+
+ tdmin_a: tdmin_a {
+ mux { /* GPIOZ_9 */
+ groups = "tdma_din2_z";
+ function = "tdma_in";
+ };
+ };
+
+ tdmout_c: tdmout_c {
+ mux { /* GPIODV_7, GPIODV_8, GPIODV_9 */
+ groups = "tdmc_sclk",
+ "tdmc_fs",
+ "tdmc_dout0";
+ function = "tdmc_out";
+ };
+ };
+
+ tdmin_c: tdmin_c {
+ mux { /* GPIODV_10 */
+ groups = "tdmc_din1";
+ function = "tdmc_in";
+ };
+ };
+
+ spdifin_a: spdifin_a {
+ mux { /* GPIODV_5 */
+ groups = "spdif_in";
+ function = "spdif_in";
+ };
+ };
+
+ spdifout_a: spdifout_a {
+ mux { /* GPIODV_4 */
+ groups = "spdif_out_dv4";
+ function = "spdif_out";
+ };
+ };
+
+ pdmin: pdmin {
+ mux { /* GPIOZ_7, GPIOZ_8*/
+ groups = "pdm_dclk_z",
+ "pdm_din0_z";
+ function = "pdm";
+ };
+ };
+
+
+}; /* end of pinctrl_periphs */
+
+&pinctrl_aobus {
+ spdifout: spdifout {
+ mux { /* gpiao_10 */
+ groups = "spdif_out_ao";
+ function = "spdif_out_ao";
+ };
+ };
+}; /* end of pinctrl_aobus */
+
&sd_emmc_b {
status = "okay";
sd {
caps = "MMC_CAP_4_BIT_DATA",
- "MMC_CAP_MMC_HIGHSPEED",
- "MMC_CAP_SD_HIGHSPEED",
- "MMC_CAP_NONREMOVABLE"; /**ptm debug */
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED",
+ "MMC_CAP_NONREMOVABLE"; /**ptm debug */
f_min = <400000>;
f_max = <200000000>;
};
--- /dev/null
+/*
+ * include/dt-bindings/clock/amlogic,tl1-audio-clk.h
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __TL1_AUDIO_CLK_H
+#define __TL1_AUDIO_CLK_H
+
+/*
+ * CLKID audio index values
+ */
+
+#define CLKID_AUDIO_DDR_ARB 0
+#define CLKID_AUDIO_PDM 1
+#define CLKID_AUDIO_TDMINA 2
+#define CLKID_AUDIO_TDMINB 3
+#define CLKID_AUDIO_TDMINC 4
+#define CLKID_AUDIO_TDMINLB 5
+#define CLKID_AUDIO_TDMOUTA 6
+#define CLKID_AUDIO_TDMOUTB 7
+#define CLKID_AUDIO_TDMOUTC 8
+#define CLKID_AUDIO_FRDDRA 9
+#define CLKID_AUDIO_FRDDRB 10
+#define CLKID_AUDIO_FRDDRC 11
+#define CLKID_AUDIO_TODDRA 12
+#define CLKID_AUDIO_TODDRB 13
+#define CLKID_AUDIO_TODDRC 14
+#define CLKID_AUDIO_LOOPBACKA 15
+#define CLKID_AUDIO_SPDIFIN 16
+#define CLKID_AUDIO_SPDIFOUT 17
+#define CLKID_AUDIO_RESAMPLEA 18
+#define CLKID_AUDIO_RESERVED0 19
+#define CLKID_AUDIO_RESERVED1 20
+#define CLKID_AUDIO_SPDIFOUTB 21
+#define CLKID_AUDIO_EQDRC 22
+#define CLKID_AUDIO_RESAMPLEB 23
+#define CLKID_AUDIO_TOVAD 24
+#define CLKID_AUDIO_AUDIOLOCKER 25
+#define CLKID_AUDIO_SPDIFIN_LB 26
+#define CLKID_AUDIO_FRATV 27
+#define CLKID_AUDIO_FRHDMIRX 28
+#define CLKID_AUDIO_FRDDRD 29
+#define CLKID_AUDIO_TODDRD 30
+#define CLKID_AUDIO_LOOPBACKB 31
+
+#define MCLK_BASE 32
+#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0)
+#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1)
+#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2)
+#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3)
+#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4)
+#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5)
+
+#define CLKID_AUDIO_SPDIFIN_CTRL (MCLK_BASE + 6)
+#define CLKID_AUDIO_SPDIFOUT_CTRL (MCLK_BASE + 7)
+#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 8)
+#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 9)
+#define CLKID_AUDIO_SPDIFOUTB_CTRL (MCLK_BASE + 10)
+#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 11)
+#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 12)
+#define CLKID_AUDIO_RESAMPLE_CTRL (MCLK_BASE + 13)
+
+#define NUM_AUDIO_CLKS (MCLK_BASE + 14)
+#endif /* __G12A_AUDIO_CLK_H */
audio_clks.o \
axg,clocks.o \
g12a,clocks.o \
+ tl1,clocks.o \
card.o \
card_utils.o \
tdm.o \
effects_hw.o \
pwrdet.o \
pwrdet_hw.o \
- sharebuffer.o
+ sharebuffer.o \
+ extn.o \
+ frhdmirx_hw.o
.compatible = "amlogic, g12a-audio-clocks",
.data = &g12a_audio_clks_init,
},
+ {
+ .compatible = "amlogic, tl1-audio-clocks",
+ .data = &tl1_audio_clks_init,
+ },
{},
};
MODULE_DEVICE_TABLE(of, audio_clocks_of_match);
extern struct audio_clk_init axg_audio_clks_init;
extern struct audio_clk_init g12a_audio_clks_init;
+extern struct audio_clk_init tl1_audio_clks_init;
struct clk_chipinfo {
/* force clock source as oscin(24M) */
platform_set_drvdata(pdev, actrl);
/* gate on all clks on bringup stage, need gate separately */
- aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN, 0xffffff);
+ aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN0, 0xffffff);
return 0;
}
return ret;
}
+ ret = card_add_ddr_kcontrols(card);
+ if (ret < 0) {
+ pr_err("Failed to add ddr controls\n");
+ return ret;
+ }
+
return snd_soc_add_card_controls(card,
snd_auge_controls, ARRAY_SIZE(snd_auge_controls));
clk_set_rate(lb_cfg->tdmin_mpll, mpll_freq);
pr_info("mpll freq:%d, %lu\n", mpll_freq,
clk_get_rate(lb_cfg->tdmin_mpll));
- offset = EE_AUDIO_MCLK_B_CTRL - EE_AUDIO_MCLK_A_CTRL;
- reg = EE_AUDIO_MCLK_A_CTRL + offset * clk_id;
+ offset = EE_AUDIO_MCLK_B_CTRL(0) - EE_AUDIO_MCLK_A_CTRL(0);
+ reg = EE_AUDIO_MCLK_A_CTRL(0) + offset * clk_id;
audiobus_write(reg,
1 << 31 | /*clk enable*/
clk_id << 24 | /*clk src*/
| tdmout_id << 0 /* mclk */
);
}
+
+void fratv_enable(bool enable)
+{
+ /* Need reset firstlry ? */
+ if (enable) {
+ audiobus_update_bits(EE_AUDIO_FRATV_CTRL0,
+ 0x1 << 29,
+ 0x1 << 29);
+ audiobus_update_bits(EE_AUDIO_FRATV_CTRL0,
+ 0x1 << 28,
+ 0x1 << 28);
+ } else
+ audiobus_update_bits(EE_AUDIO_FRATV_CTRL0,
+ 0x3 << 28,
+ 0x0 << 28);
+
+ audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, 0x1 << 31, enable << 31);
+}
+
+/* source select
+ * 0: select from ATV;
+ * 1: select from ADEC;
+ */
+void fratv_src_select(int src)
+{
+ audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, 0x1 << 20, (bool)src << 20);
+}
extern void audio_locker_set(int enable);
extern int audio_locker_get(void);
+
+extern void fratv_enable(bool enable);
+extern void fratv_src_select(int src);
#endif
"i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g",
"i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"};
-CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 0);
-CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 1);
-CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 2);
-CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 3);
-CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 4);
-CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 5);
-CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 6);
-CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 7);
-CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 8);
-CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 9);
-CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 10);
-CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 11);
-CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 12);
-CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 13);
-CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 14);
-CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 15);
-CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 16);
-CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 17);
-CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 18);
-CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 19);
+CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0);
+CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1);
+CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2);
+CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3);
+CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4);
+CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5);
+CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6);
+CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7);
+CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8);
+CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9);
+CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10);
+CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11);
+CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12);
+CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13);
+CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14);
+CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15);
+CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16);
+CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17);
+CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18);
+CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19);
static struct clk_gate *axg_audio_clk_gates[] = {
&audio_ddr_arb,
}
/* mclk_a */
-CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 31);
+CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 31);
/* mclk_b */
-CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 31);
+CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 31);
/* mclk_c */
-CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 31);
+CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 31);
/* mclk_d */
-CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 31);
+CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 31);
/* mclk_e */
-CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 31);
+CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 31);
/* mclk_f */
-CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 31);
+CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 31);
/* spdifin */
CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24);
CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8);
CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8);
CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15);
/* resample*/
-CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0xf, 24);
+CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24);
/* div is fake */
-CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0, 0);
-CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 31);
+CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 0);
+CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31);
static int axg_clks_init(struct clk **clks, void __iomem *iobase)
{
aml_priv_to_props(priv, rtd->num);
unsigned int mclk = 0, mclk_fs = 0;
int i = 0, ret = 0;
- int clk_dir = 0;
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- clk_dir = SND_SOC_CLOCK_OUT;
- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
- clk_dir = SND_SOC_CLOCK_IN;
+ int clk_idx = substream->stream;
if (priv->mclk_fs)
mclk_fs = priv->mclk_fs;
for (i = 0; i < rtd->num_codecs; i++) {
codec_dai = rtd->codec_dais[i];
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
- clk_dir);
+ SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP)
goto err;
}
- ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
- clk_dir);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, clk_idx, mclk,
+ SND_SOC_CLOCK_OUT);
if (ret && ret != -ENOTSUPP)
goto err;
.eqdrc_fn = true,
};
+static struct aml_chipset_info tl1_chipset_info = {
+ .spdif_b = true,
+};
+
static const struct of_device_id auge_of_match[] = {
{
.compatible = "amlogic, axg-sound-card",
.compatible = "amlogic, g12a-sound-card",
.data = &g12a_chipset_info,
},
+ {
+ .compatible = "amlogic, tl1-sound-card",
+ .data = &tl1_chipset_info,
+ },
{},
};
MODULE_DEVICE_TABLE(of, auge_of_match);
if (ret >= 0)
return ret;
err:
+ pr_err("%s error ret:%d\n", __func__, ret);
aml_card_clean_reference(&priv->snd_card);
return ret;
#endif
struct ddr_chipinfo {
- /* INT and Start address separated */
- bool addr_separated;
+ /* INT and Start address is same or separated */
+ bool int_start_same_addr;
/* force finished */
bool force_finished;
/* same source */
bool same_src_fn;
/* insert channel number */
bool insert_chnum;
+ /* source sel switch to ctrl1
+ * for toddr, 0: source sel is controlled by ctrl0
+ * 1: source sel is controlled by ctrl1
+ * for frddr, 0: source sel is controlled by ctrl0
+ * 1: source sel is controlled by ctrl2
+ */
+ bool src_sel_ctrl;
+ /* toddr number max
+ * 0: default, 3 toddr, axg, g12a, g12b
+ * 4: 4 toddr, tl1
+ */
+ int fifo_num;
};
struct toddr {
struct ddr_chipinfo *chipinfo;
};
-#define DDRMAX 3
+#define DDRMAX 4
static struct frddr frddrs[DDRMAX];
static struct toddr toddrs[DDRMAX];
/* int address */
if (to->chipinfo
- && to->chipinfo->addr_separated) {
+ && (!to->chipinfo->int_start_same_addr)) {
reg = calc_toddr_address(EE_AUDIO_TODDR_A_INIT_ADDR, reg_base);
aml_audiobus_write(actrl, reg, start);
}
src = LOOPBACK;
}
- reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base);
- aml_audiobus_update_bits(actrl, reg, 0x7, src & 0x7);
+ if (to->chipinfo
+ && to->chipinfo->src_sel_ctrl) {
+ reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base);
+ aml_audiobus_update_bits(actrl, reg,
+ 0xf << 28,
+ (src & 0xf) << 28);
+ } else {
+ reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base);
+ aml_audiobus_update_bits(actrl, reg, 0x7, src & 0x7);
+ }
}
void aml_toddr_set_fifos(struct toddr *to, unsigned int thresh)
{
struct aml_audio_controller *actrl = to->actrl;
unsigned int reg_base = to->reg_base;
- unsigned int reg;
+ unsigned int reg, mask, val;
reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base);
- aml_audiobus_write(actrl, reg, (thresh-1)<<16|2<<8);
+
+ if (to->chipinfo
+ && to->chipinfo->src_sel_ctrl) {
+ mask = 0xfff << 12 | 0xf << 8;
+ val = (thresh-1) << 12 | 2 << 8;
+ } else {
+ mask = 0xff << 16 | 0xf << 8;
+ val = (thresh-1) << 16 | 2 << 8;
+ }
+
+ aml_audiobus_update_bits(actrl, reg, mask, val);
}
void aml_toddr_set_format(struct toddr *to, struct toddr_fmt *fmt)
/* int address */
if (fr->chipinfo
- && fr->chipinfo->addr_separated) {
+ && (!fr->chipinfo->int_start_same_addr)) {
reg = calc_frddr_address(EE_AUDIO_FRDDR_A_INIT_ADDR, reg_base);
aml_audiobus_write(actrl, reg, start);
}
{
struct aml_audio_controller *actrl = fr->actrl;
unsigned int reg_base = fr->reg_base;
- unsigned int reg;
+ unsigned int reg, src_sel_en;
fr->dest = dst;
- reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base);
- aml_audiobus_update_bits(actrl, reg, 0x7, dst & 0x7);
+ if (fr->chipinfo
+ && fr->chipinfo->src_sel_ctrl) {
+ reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL2, reg_base);
+ src_sel_en = 4;
+ } else {
+ reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base);
+ src_sel_en = 3;
+ }
+
+ aml_audiobus_update_bits(actrl, reg, 0x7, dst & 0x7);
/* same source en */
if (fr->chipinfo
&& fr->chipinfo->same_src_fn) {
- aml_audiobus_update_bits(actrl, reg, 1 << 3, 1 << 3);
+ aml_audiobus_update_bits(actrl, reg,
+ 1 << src_sel_en, 1 << src_sel_en);
}
}
audiobus_write(reg, 0x0);
}
+static int toddr_src_idx = -1;
+
+static const char *const toddr_src_sel_texts[] = {
+ "TDMIN_A", "TDMIN_B", "TDMIN_C", "SPDIFIN",
+ "PDMIN", "FRATV", "TDMIN_LB", "LOOPBACK_A",
+ "FRHDMIRX", "LOOPBACK_B", "SPDIFIN_LB",
+ "RESERVED", "RESERVED", "RESERVED", "RESERVED",
+ "VAD"
+};
+
+static const struct soc_enum toddr_input_source_enum =
+ SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(toddr_src_sel_texts),
+ toddr_src_sel_texts);
+
+int toddr_src_get(void)
+{
+ return toddr_src_idx;
+}
+
+const char *toddr_src_get_str(int idx)
+{
+ if (idx < 0 || idx > 15)
+ return NULL;
+
+ return toddr_src_sel_texts[idx];
+}
+
+static int toddr_src_enum_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.enumerated.item[0] = toddr_src_idx;
+
+ return 0;
+}
+
+static int toddr_src_enum_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ toddr_src_idx = ucontrol->value.enumerated.item[0];
+
+ return 0;
+}
+
+static int frddr_src_idx = -1;
+
+static const char *const frddr_src_sel_texts[] = {
+ "TDMOUT_A", "TDMOUT_B", "TDMOUT_C", "SPDIFOUT", "SPDIFOUT_B"
+};
+
+static const struct soc_enum frddr_output_source_enum =
+ SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(frddr_src_sel_texts),
+ frddr_src_sel_texts);
+
+int frddr_src_get(void)
+{
+ return frddr_src_idx;
+}
+
+const char *frddr_src_get_str(int idx)
+{
+ if (idx < 0 || idx > 4)
+ return NULL;
+
+ return frddr_src_sel_texts[idx];
+}
+
+static int frddr_src_enum_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.enumerated.item[0] = frddr_src_idx;
+
+ return 0;
+}
+
+static int frddr_src_enum_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ frddr_src_idx = ucontrol->value.enumerated.item[0];
+
+ return 0;
+}
+
+static const struct snd_kcontrol_new snd_ddr_controls[] = {
+ SOC_ENUM_EXT("Audio In Source",
+ toddr_input_source_enum,
+ toddr_src_enum_get,
+ toddr_src_enum_set),
+ SOC_ENUM_EXT("Audio Out Sink",
+ toddr_input_source_enum,
+ frddr_src_enum_get,
+ frddr_src_enum_set),
+};
+
+int card_add_ddr_kcontrols(struct snd_soc_card *card)
+{
+ unsigned int idx;
+ int err;
+
+ for (idx = 0; idx < ARRAY_SIZE(snd_ddr_controls); idx++) {
+ err = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&snd_ddr_controls[idx],
+ NULL));
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static struct ddr_chipinfo axg_ddr_chipinfo = {
+ .int_start_same_addr = true,
+};
+
static struct ddr_chipinfo g12a_ddr_chipinfo = {
- .addr_separated = true,
.same_src_fn = true,
};
+static struct ddr_chipinfo tl1_ddr_chipinfo = {
+ .same_src_fn = true,
+ .src_sel_ctrl = true,
+ .fifo_num = 4,
+};
static const struct of_device_id aml_ddr_mngr_device_id[] = {
{
.compatible = "amlogic, axg-audio-ddr-manager",
+ .data = &axg_ddr_chipinfo,
},
{
.compatible = "amlogic, g12a-audio-ddr-manager",
.data = &g12a_ddr_chipinfo,
},
+ {
+ .compatible = "amlogic, tl1-audio-ddr-manager",
+ .data = &tl1_ddr_chipinfo,
+ },
{},
};
MODULE_DEVICE_TABLE(of, aml_ddr_mngr_device_id);
static int aml_ddr_mngr_platform_probe(struct platform_device *pdev)
{
struct ddr_chipinfo *p_ddr_chipinfo;
+ int ddr_num = 3; /* early chipset support max 3 ddr num */
int i;
p_ddr_chipinfo = (struct ddr_chipinfo *)
frddrs[DDR_B].irq = platform_get_irq_byname(pdev, "frddr_b");
frddrs[DDR_C].irq = platform_get_irq_byname(pdev, "frddr_c");
- for (i = 0; i < DDRMAX; i++) {
+ if (p_ddr_chipinfo
+ && (p_ddr_chipinfo->fifo_num == 4)) {
+ toddrs[DDR_D].irq = platform_get_irq_byname(pdev, "toddr_d");
+ frddrs[DDR_D].irq = platform_get_irq_byname(pdev, "frddr_d");
+ ddr_num = p_ddr_chipinfo->fifo_num;
+ }
+
+ for (i = 0; i < ddr_num; i++) {
pr_info("%d, irqs toddr %d, frddr %d\n",
i, toddrs[i].irq, frddrs[i].irq);
if (toddrs[i].irq <= 0 || frddrs[i].irq <= 0) {
frddrs[DDR_B].fifo_id = DDR_B;
frddrs[DDR_C].fifo_id = DDR_C;
- toddrs[DDR_A].chipinfo = p_ddr_chipinfo;
- toddrs[DDR_B].chipinfo = p_ddr_chipinfo;
- toddrs[DDR_C].chipinfo = p_ddr_chipinfo;
- frddrs[DDR_A].chipinfo = p_ddr_chipinfo;
- frddrs[DDR_B].chipinfo = p_ddr_chipinfo;
- frddrs[DDR_C].chipinfo = p_ddr_chipinfo;
+ if (p_ddr_chipinfo) {
+ toddrs[DDR_A].chipinfo = p_ddr_chipinfo;
+ toddrs[DDR_B].chipinfo = p_ddr_chipinfo;
+ toddrs[DDR_C].chipinfo = p_ddr_chipinfo;
+ frddrs[DDR_A].chipinfo = p_ddr_chipinfo;
+ frddrs[DDR_B].chipinfo = p_ddr_chipinfo;
+ frddrs[DDR_C].chipinfo = p_ddr_chipinfo;
+
+ if (p_ddr_chipinfo->fifo_num == 4) {
+ toddrs[DDR_D].reg_base = EE_AUDIO_TODDR_D_CTRL0;
+ toddrs[DDR_D].fifo_id = DDR_D;
+ frddrs[DDR_D].reg_base = EE_AUDIO_FRDDR_D_CTRL0;
+ frddrs[DDR_D].fifo_id = DDR_D;
+ }
+ }
return 0;
}
#include <linux/device.h>
#include <linux/interrupt.h>
+#include <sound/soc.h>
#include "audio_io.h"
enum ddr_num {
DDR_A,
DDR_B,
DDR_C,
+ DDR_D,
};
enum ddr_types {
RJ_32BITS,
};
+/*
+ * from tl1, add new source FRATV, FRHDMIRX, LOOPBACK_B, SPDIFIN_LB, VAD
+ */
enum toddr_src {
TDMIN_A,
TDMIN_B,
TDMIN_C,
SPDIFIN,
PDMIN,
- NONE,
+ FRATV, /* NONE for axg, g12a, g12b */
TDMIN_LB,
LOOPBACK,
+ FRHDMIRX, /* from tl1 chipset*/
+ LOOPBACK_B,
+ SPDIFIN_LB,
+ VAD,
};
enum frddr_dest {
void frddr_init_without_mngr(unsigned int frddr_index, unsigned int src0_sel);
void frddr_deinit_without_mngr(unsigned int frddr_index);
+
+int toddr_src_get(void);
+const char *toddr_src_get_str(int idx);
+int frddr_src_get(void);
+const char *frddr_src_get_str(int idx);
+
+int card_add_ddr_kcontrols(struct snd_soc_card *card);
+
#endif
* 1:multiply gain after ng
*/
SOC_SINGLE_EXT_TLV("EQ Volume Pos",
- AED_EQ_VOLUME, 28, 0x1, 0,
+ AED_EQ_VOLUME_G12X, 28, 0x1, 0,
mixer_eqdrc_read, mixer_eqdrc_write,
NULL),
SOC_SINGLE_EXT_TLV("EQ master volume",
- AED_EQ_VOLUME, 16, 0x3FF, 1,
+ AED_EQ_VOLUME_G12X, 16, 0x3FF, 1,
mixer_eqdrc_read, mixer_eqdrc_write,
mvol_tlv),
SOC_SINGLE_EXT_TLV("EQ ch1 volume",
- AED_EQ_VOLUME, 8, 0xFF, 1,
+ AED_EQ_VOLUME_G12X, 8, 0xFF, 1,
mixer_eqdrc_read, mixer_eqdrc_write,
chvol_tlv),
SOC_SINGLE_EXT_TLV("EQ ch2 volume",
- AED_EQ_VOLUME, 0, 0xFF, 1,
+ AED_EQ_VOLUME_G12X, 0, 0xFF, 1,
mixer_eqdrc_read, mixer_eqdrc_write,
chvol_tlv),
SOC_SINGLE_EXT("EQ master volume mute",
- AED_MUTE, 31, 0x1, 0,
+ AED_MUTE_G12X, 31, 0x1, 0,
mixer_eqdrc_read, mixer_eqdrc_write),
SOC_SINGLE_EXT("EQ/DRC Channel Mask",
mixer_eqdrc_read, mixer_set_AED_req_ctrl),
SOC_SINGLE_EXT("EQ enable",
- AED_EQ_EN, 0, 0x1, 0,
+ AED_EQ_EN_G12X, 0, 0x1, 0,
mixer_eqdrc_read, mixer_set_EQ),
SOC_SINGLE_EXT("DRC enable",
int DRC0_enable(int enable, int thd0, int k0)
{
if (enable == 1) {
- eqdrc_write(AED_DRC_THD0, thd0/*aml_drc_tko_table[2]*/);
- eqdrc_write(AED_DRC_K0, k0/*aml_drc_tko_table[4]*/);
+ eqdrc_write(AED_DRC_THD0_G12X, thd0/*aml_drc_tko_table[2]*/);
+ eqdrc_write(AED_DRC_K0_G12X, k0/*aml_drc_tko_table[4]*/);
} else {
- eqdrc_write(AED_DRC_THD0, 0xbf000000);
- eqdrc_write(AED_DRC_K0, 0x40000);
+ eqdrc_write(AED_DRC_THD0_G12X, 0xbf000000);
+ eqdrc_write(AED_DRC_K0_G12X, 0x40000);
}
return 0;
unsigned int channel_1_volume,
unsigned int channel_2_volume)
{
- eqdrc_write(AED_EQ_VOLUME, (0 << 30) /* volume step: 0.125dB*/
+ eqdrc_write(AED_EQ_VOLUME_G12X, (0 << 30) /* volume step: 0.125dB*/
| (master_volume << 16) /* master volume: 0dB*/
| (channel_1_volume << 8) /* channel 1 volume: 0dB*/
| (channel_2_volume << 0) /* channel 2 volume: 0dB*/
);
- eqdrc_write(AED_EQ_VOLUME_SLEW_CNT, 0x40);
- eqdrc_write(AED_MUTE, 0);
+ eqdrc_write(AED_EQ_VOLUME_SLEW_CNT_G12X, 0x40);
+ eqdrc_write(AED_MUTE_G12X, 0);
return 0;
}
}
}
- eqdrc_update_bits(AED_EQ_EN, 1, enable);
+ eqdrc_update_bits(AED_EQ_EN_G12X, 1, enable);
}
void aed_set_drc(int enable, int drc_len, unsigned int *drc_params,
--- /dev/null
+/*
+ * sound/soc/amlogic/auge/extn.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * Audio External Input/Out drirver
+ * such as fratv, frhdmirx
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/ioctl.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/initval.h>
+#include <sound/control.h>
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+
+#include "ddr_mngr.h"
+#include "audio_utils.h"
+#include "frhdmirx_hw.h"
+
+#define DRV_NAME "EXTN"
+
+struct extn {
+ struct aml_audio_controller *actrl;
+ struct device *dev;
+ unsigned int sysclk_freq;
+
+ int irq_frhdmirx;
+
+ struct toddr *tddr;
+ struct frddr *fddr;
+};
+
+#define PREALLOC_BUFFER (32 * 1024)
+#define PREALLOC_BUFFER_MAX (256 * 1024)
+
+#define EXTN_RATES (SNDRV_PCM_RATE_8000_192000)
+#define EXTN_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static const struct snd_pcm_hardware extn_hardware = {
+ .info =
+ SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE,
+
+ .formats = EXTN_FORMATS,
+
+ .period_bytes_min = 64,
+ .period_bytes_max = 128 * 1024,
+ .periods_min = 2,
+ .periods_max = 1024,
+ .buffer_bytes_max = 256 * 1024,
+
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 32,
+};
+
+static irqreturn_t extn_ddr_isr(int irq, void *devid)
+{
+ struct snd_pcm_substream *substream =
+ (struct snd_pcm_substream *)devid;
+
+ if (!snd_pcm_running(substream))
+ return IRQ_HANDLED;
+
+ snd_pcm_period_elapsed(substream);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t frhdmirx_isr(int irq, void *devid)
+{
+ return IRQ_HANDLED;
+}
+
+static int extn_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct device *dev = rtd->platform->dev;
+ struct extn *p_extn;
+
+ pr_info("asoc debug: %s-%d\n", __func__, __LINE__);
+
+ p_extn = (struct extn *)dev_get_drvdata(dev);
+
+ snd_soc_set_runtime_hwparams(substream, &extn_hardware);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ p_extn->fddr = aml_audio_register_frddr(dev,
+ p_extn->actrl,
+ extn_ddr_isr, substream);
+ if (p_extn->fddr == NULL) {
+ dev_err(dev, "failed to claim from ddr\n");
+ return -ENXIO;
+ }
+ } else {
+ p_extn->tddr = aml_audio_register_toddr(dev,
+ p_extn->actrl,
+ extn_ddr_isr, substream);
+ if (p_extn->tddr == NULL) {
+ dev_err(dev, "failed to claim to ddr\n");
+ return -ENXIO;
+ }
+
+ if (toddr_src_get() == FRHDMIRX) {
+ int ret = request_irq(p_extn->irq_frhdmirx,
+ frhdmirx_isr, 0, "irq_frhdmirx",
+ p_extn);
+ if (ret) {
+ dev_err(p_extn->dev, "failed to claim irq_frhdmirx %u\n",
+ p_extn->irq_frhdmirx);
+ return -ENXIO;
+ }
+ }
+ }
+
+ runtime->private_data = p_extn;
+
+ return 0;
+}
+
+static int extn_close(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct extn *p_extn = runtime->private_data;
+
+ pr_info("asoc debug: %s-%d\n", __func__, __LINE__);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ aml_audio_unregister_frddr(p_extn->dev, substream);
+ else {
+ aml_audio_unregister_toddr(p_extn->dev, substream);
+
+ if (toddr_src_get() == FRHDMIRX)
+ free_irq(p_extn->irq_frhdmirx, p_extn);
+ }
+ runtime->private_data = NULL;
+
+ return 0;
+}
+
+static int extn_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *hw_params)
+{
+ return snd_pcm_lib_malloc_pages(substream,
+ params_buffer_bytes(hw_params));
+}
+
+static int extn_hw_free(struct snd_pcm_substream *substream)
+{
+ snd_pcm_lib_free_pages(substream);
+
+ return 0;
+}
+
+static int extn_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ return 0;
+}
+
+static int extn_prepare(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct extn *p_extn = runtime->private_data;
+ unsigned int start_addr, end_addr, int_addr;
+
+ start_addr = runtime->dma_addr;
+ end_addr = start_addr + runtime->dma_bytes - 8;
+ int_addr = frames_to_bytes(runtime, runtime->period_size) / 8;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ struct frddr *fr = p_extn->fddr;
+
+ aml_frddr_set_buf(fr, start_addr, end_addr);
+ aml_frddr_set_intrpt(fr, int_addr);
+ } else {
+ struct toddr *to = p_extn->tddr;
+
+ aml_toddr_set_buf(to, start_addr, end_addr);
+ aml_toddr_set_intrpt(to, int_addr);
+ }
+
+ return 0;
+}
+
+static snd_pcm_uframes_t extn_pointer(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct extn *p_extn = runtime->private_data;
+ unsigned int addr, start_addr;
+ snd_pcm_uframes_t frames;
+
+ start_addr = runtime->dma_addr;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ addr = aml_frddr_get_position(p_extn->fddr);
+ else
+ addr = aml_toddr_get_position(p_extn->tddr);
+
+ frames = bytes_to_frames(runtime, addr - start_addr);
+ if (frames > runtime->buffer_size)
+ frames = 0;
+
+ return frames;
+}
+
+int extn_silence(struct snd_pcm_substream *substream, int channel,
+ snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ char *ppos;
+ int n;
+
+ n = frames_to_bytes(runtime, count);
+ ppos = runtime->dma_area + frames_to_bytes(runtime, pos);
+ memset(ppos, 0, n);
+
+ return 0;
+}
+
+static int extn_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ return snd_pcm_lib_default_mmap(substream, vma);
+}
+
+static struct snd_pcm_ops extn_ops = {
+ .open = extn_open,
+ .close = extn_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = extn_hw_params,
+ .hw_free = extn_hw_free,
+ .prepare = extn_prepare,
+ .trigger = extn_trigger,
+ .pointer = extn_pointer,
+ .silence = extn_silence,
+ .mmap = extn_mmap,
+};
+
+static int extn_new(struct snd_soc_pcm_runtime *rtd)
+{
+ return snd_pcm_lib_preallocate_pages_for_all(
+ rtd->pcm, SNDRV_DMA_TYPE_DEV,
+ rtd->card->snd_card->dev,
+ PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
+}
+
+struct snd_soc_platform_driver extn_platform = {
+ .ops = &extn_ops,
+ .pcm_new = extn_new,
+};
+
+static int extn_dai_probe(struct snd_soc_dai *cpu_dai)
+{
+ pr_info("asoc debug: %s-%d\n", __func__, __LINE__);
+
+ return 0;
+}
+
+static int extn_dai_remove(struct snd_soc_dai *cpu_dai)
+{
+ return 0;
+}
+
+static int extn_dai_startup(
+ struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ return 0;
+}
+
+static void extn_dai_shutdown(
+ struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+}
+
+static int extn_dai_prepare(
+ struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int bit_depth = snd_pcm_format_width(runtime->format);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ struct frddr *fr = p_extn->fddr;
+ enum frddr_dest dst = frddr_src_get();
+
+ pr_info("%s Expected frddr dst:%s\n",
+ __func__,
+ frddr_src_get_str(dst));
+
+ aml_frddr_select_dst(fr, dst);
+ aml_frddr_set_fifos(fr, 0x40, 0x20);
+ } else {
+ struct toddr *to = p_extn->tddr;
+ unsigned int msb = 32 - 1;
+ unsigned int lsb = 32 - bit_depth;
+ unsigned int toddr_type;
+ unsigned int src = toddr_src_get();
+ struct toddr_fmt fmt;
+
+ switch (bit_depth) {
+ case 8:
+ case 16:
+ case 32:
+ toddr_type = 0;
+ break;
+ case 24:
+ toddr_type = 4;
+ break;
+ default:
+ pr_err("invalid bit_depth: %d\n", bit_depth);
+ return -EINVAL;
+ }
+
+ pr_info("%s Expected toddr src:%s\n",
+ __func__,
+ toddr_src_get_str(src));
+
+ if (src == FRATV)
+ fratv_src_select(0);
+ else if (src == FRHDMIRX) {
+ frhdmirx_ctrl(runtime->channels, 0);
+ frhdmirx_src_select(0);
+ }
+
+ fmt.type = toddr_type;
+ fmt.msb = msb;
+ fmt.lsb = lsb;
+ fmt.endian = 0;
+ fmt.bit_depth = bit_depth;
+ fmt.ch_num = runtime->channels;
+ fmt.rate = runtime->rate;
+
+ aml_toddr_select_src(to, src);
+ aml_toddr_set_format(to, &fmt);
+ aml_toddr_set_fifos(to, 0x40);
+ }
+
+ return 0;
+}
+
+static int extn_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int src = toddr_src_get();
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ dev_info(substream->pcm->card->dev, "External Playback enable\n");
+
+ aml_frddr_enable(p_extn->fddr, true);
+ } else {
+ dev_info(substream->pcm->card->dev, "External Capture enable\n");
+
+ if (src == FRATV)
+ fratv_enable(true);
+ else if (src == FRHDMIRX)
+ frhdmirx_enable(true);
+
+ aml_toddr_enable(p_extn->tddr, true);
+ }
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ dev_info(substream->pcm->card->dev, "External Playback disable\n");
+
+ aml_frddr_enable(p_extn->fddr, false);
+ } else {
+ dev_info(substream->pcm->card->dev, "External Capture disable\n");
+
+ if (src == FRATV)
+ fratv_enable(false);
+ else if (src == FRHDMIRX)
+ frhdmirx_enable(false);
+
+ aml_toddr_enable(p_extn->tddr, false);
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int extn_dai_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int rate = params_rate(params);
+ int ret = 0;
+
+ pr_info("%s:rate:%d, sysclk:%d\n",
+ __func__,
+ rate,
+ p_extn->sysclk_freq);
+
+ return ret;
+}
+
+static int extn_dai_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+ struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai);
+
+ pr_info("asoc extn_dai_set_fmt, %#x, %p\n", fmt, p_extn);
+
+ return 0;
+}
+
+static int extn_dai_set_sysclk(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai);
+
+ p_extn->sysclk_freq = freq;
+ pr_info("extn_dai_set_sysclk, %d, %d, %d\n",
+ clk_id, freq, dir);
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops extn_dai_ops = {
+ .startup = extn_dai_startup,
+ .shutdown = extn_dai_shutdown,
+ .prepare = extn_dai_prepare,
+ .trigger = extn_dai_trigger,
+ .hw_params = extn_dai_hw_params,
+ .set_fmt = extn_dai_set_fmt,
+ .set_sysclk = extn_dai_set_sysclk,
+};
+
+static struct snd_soc_dai_driver extn_dai[] = {
+ {
+ .name = "EXTN",
+ .id = 0,
+ .probe = extn_dai_probe,
+ .remove = extn_dai_remove,
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 32,
+ .rates = EXTN_RATES,
+ .formats = EXTN_FORMATS,
+ },
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 32,
+ .rates = EXTN_RATES,
+ .formats = EXTN_FORMATS,
+ },
+ .ops = &extn_dai_ops,
+ },
+};
+
+static const struct snd_soc_component_driver extn_component = {
+ .name = DRV_NAME,
+};
+
+static const struct of_device_id extn_device_id[] = {
+ {
+ .compatible = "amlogic, snd-extn",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, extn_device_id);
+
+static int extn_platform_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *node_prt = NULL;
+ struct platform_device *pdev_parent;
+ struct device *dev = &pdev->dev;
+ struct aml_audio_controller *actrl = NULL;
+ struct extn *extn = NULL;
+ int ret = 0;
+
+
+ extn = devm_kzalloc(dev, sizeof(struct extn), GFP_KERNEL);
+ if (!extn)
+ return -ENOMEM;
+
+ extn->dev = dev;
+ dev_set_drvdata(dev, extn);
+
+ /* get audio controller */
+ node_prt = of_get_parent(node);
+ if (node_prt == NULL)
+ return -ENXIO;
+
+ pdev_parent = of_find_device_by_node(node_prt);
+ of_node_put(node_prt);
+ actrl = (struct aml_audio_controller *)
+ platform_get_drvdata(pdev_parent);
+ extn->actrl = actrl;
+
+ /* irqs */
+ extn->irq_frhdmirx = platform_get_irq_byname(pdev, "irq_frhdmirx");
+ if (extn->irq_frhdmirx < 0) {
+ dev_err(dev, "Failed to get irq_frhdmirx:%d\n",
+ extn->irq_frhdmirx);
+ return -ENXIO;
+ }
+
+ ret = snd_soc_register_component(&pdev->dev,
+ &extn_component,
+ extn_dai,
+ ARRAY_SIZE(extn_dai));
+ if (ret) {
+ dev_err(&pdev->dev,
+ "snd_soc_register_component failed\n");
+ return ret;
+ }
+
+ pr_info("%s, register soc platform\n", __func__);
+
+ return devm_snd_soc_register_platform(dev, &extn_platform);
+}
+
+struct platform_driver extn_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = extn_device_id,
+ },
+ .probe = extn_platform_probe,
+};
+module_platform_driver(extn_driver);
+
+MODULE_AUTHOR("Amlogic, Inc.");
+MODULE_DESCRIPTION("Amlogic External Input/Output ASoc driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("Platform:" DRV_NAME);
+MODULE_DEVICE_TABLE(of, extn_device_id);
--- /dev/null
+/*
+ * sound/soc/amlogic/auge/frhdmirx_hw.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <linux/types.h>
+
+#include "frhdmirx_hw.h"
+#include "regs.h"
+#include "iomap.h"
+
+void frhdmirx_enable(bool enable)
+{
+ if (enable) {
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0,
+ 0x1 << 29,
+ 0x1 << 29);
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0,
+ 0x1 << 28,
+ 0x1 << 28);
+ } else
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0,
+ 0x3 << 28,
+ 0x0 << 28);
+
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, 0x1 << 31, enable << 31);
+}
+
+/* source select
+ * 0: select spdif lane;
+ * 1: select PAO mode;
+ */
+void frhdmirx_src_select(int src)
+{
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0,
+ 0x1 << 23,
+ (bool)src << 23);
+}
+
+void frhdmirx_enable_irq_bits(int channels, int src)
+{
+ int lane, int_bits = 0, i;
+
+ if (channels % 2)
+ lane = channels / 2 + 1;
+ else
+ lane = channels / 2;
+
+ /* interrupt bits */
+ if (src) { /* PAO mode */
+ int_bits = (0x1 << 24 | /* PAO data: find papb */
+ 0x1 << 16 /* PAO data: find pcpd changed */
+ );
+ } else { /* SPDIF Lane*/
+ int lane_irq_bits = (0x1 << 7 | /* lane: find papb */
+ 0x1 << 6 | /* lane: find papb */
+ 0x1 << 5 | /* lane: find nonpcm to pcm */
+ 0x1 << 4 | /* lane: find pcpd changed */
+ 0x1 << 3 | /* lane: find ch status changed */
+ 0x1 << 1 /* lane: find parity error */
+ );
+
+ for (i = 0; i < lane; i++)
+ int_bits |= (lane_irq_bits << i);
+ }
+ audiobus_write(EE_AUDIO_FRHDMIRX_CTRL2, int_bits);
+}
+
+void frhdmirx_ctrl(int channels, int src)
+{
+ int lane, lane_mask = 0, i;
+
+ if (channels % 2)
+ lane = channels / 2 + 1;
+ else
+ lane = channels / 2;
+
+ for (i = 0; i < lane; i++)
+ lane_mask |= (1 << i);
+
+ audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0,
+ 0x1 << 30 | 0xf << 24 | 0x3 << 11,
+ 0x1 << 30 | /* chnum_sel */
+ lane_mask << 24 | /* chnum_sel */
+ 0x0 << 11 /* req_sel, Sync 4 spdifin by which */
+ );
+
+ /* nonpcm2pcm_th */
+ audiobus_write(EE_AUDIO_FRHDMIRX_CTRL1, 0xff << 20);
+
+ /* enable irq bits */
+ frhdmirx_enable_irq_bits(channels, src);
+}
--- /dev/null
+/*
+ * sound/soc/amlogic/auge/frhdmirx_hw.h
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#ifndef __FRHDMIRX_HW_H__
+#define __FRHDMIRX_HW_H__
+
+extern void frhdmirx_enable(bool enable);
+extern void frhdmirx_src_select(int src);
+extern void frhdmirx_ctrl(int channels, int src);
+
+#endif
"i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g",
"i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"};
-CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 0);
-CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 1);
-CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 2);
-CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 3);
-CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 4);
-CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 5);
-CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 6);
-CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 7);
-CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 8);
-CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 9);
-CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 10);
-CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 11);
-CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 12);
-CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 13);
-CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 14);
-CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 15);
-CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 16);
-CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 17);
-CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 18);
-CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 19);
-CLOCK_GATE(audio_toram, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 20);
-CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 21);
-CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 22);
+CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0);
+CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1);
+CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2);
+CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3);
+CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4);
+CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5);
+CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6);
+CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7);
+CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8);
+CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9);
+CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10);
+CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11);
+CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12);
+CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13);
+CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14);
+CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15);
+CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16);
+CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17);
+CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18);
+CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19);
+CLOCK_GATE(audio_toram, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 20);
+CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 21);
+CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 22);
static struct clk_gate *g12a_audio_clk_gates[] = {
&audio_ddr_arb,
}
/* mclk_a */
-CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 31);
+CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 31);
/* mclk_b */
-CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 31);
+CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 31);
/* mclk_c */
-CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 31);
+CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 31);
/* mclk_d */
-CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 31);
+CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 31);
/* mclk_e */
-CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 31);
+CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 31);
/* mclk_f */
-CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0x7, 24);
-CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0, 16);
-CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 31);
+CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0x7, 24);
+CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0, 16);
+CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 31);
/* spdifin */
CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24);
CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8);
CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8);
CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15);
/* audio resample */
-CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0xf, 24);
-CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0, 8);
-CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 31);
+CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24);
+CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 8);
+CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31);
static int g12a_clks_init(struct clk **clks, void __iomem *iobase)
{
#include "regs.h"
#include "ddr_mngr.h"
-/*#define G12A_PTM*/
+/*#define __PTM_PDM_CLK__*/
static struct snd_pcm_hardware aml_pdm_hardware = {
.info =
sysclk_srcpll_freq = clk_get_rate(p_pdm->sysclk_srcpll);
dclk_srcpll_freq = clk_get_rate(p_pdm->dclk_srcpll);
-#ifdef G12A_PTM
- clk_set_rate(p_pdm->dclk_srcpll, 24576000);
+#ifdef __PTM_PDM_CLK__
+ clk_set_rate(p_pdm->clk_pdm_sysclk, 133333351);
+ clk_set_rate(p_pdm->dclk_srcpll, 24576000 * 15); /* 350m */
+ clk_set_rate(p_pdm->clk_pdm_dclk, 3072000);
#else
clk_set_rate(p_pdm->clk_pdm_sysclk, 133333351);
};
static struct pdm_chipinfo g12a_pdm_chipinfo = {
- .mute_fn = true,
+ .mute_fn = true,
+ .truncate_data = false,
+};
+
+static struct pdm_chipinfo tl1_pdm_chipinfo = {
+ .mute_fn = true,
+ .truncate_data = true,
};
static const struct of_device_id aml_pdm_device_id[] = {
},
{
.compatible = "amlogic, g12a-snd-pdm",
- .data = &g12a_pdm_chipinfo,
+ .data = &g12a_pdm_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-pdm",
+ .data = &tl1_pdm_chipinfo,
},
{}
};
struct pdm_chipinfo {
/* pdm supports mute function */
bool mute_fn;
+ /* truncate invalid data when filter init */
+ bool truncate_data;
};
struct aml_pdm {
#ifndef __AML_REGS_H_
#define __AML_REGS_H_
-/*
- * PDM - Registers
- * PDM
- *
- * BASE_ADR 32'hFF632000
- */
-#define PDM_CTRL 0x00
-#define PDM_HCIC_CTRL1 0x01
-#define PDM_HCIC_CTRL2 0x02
-#define PDM_F1_CTRL 0x03
-#define PDM_F2_CTRL 0x04
-#define PDM_F3_CTRL 0x05
-#define PDM_HPF_CTRL 0x06
-#define PDM_CHAN_CTRL 0x07
-#define PDM_CHAN_CTRL1 0x08
-#define PDM_COEFF_ADDR 0x09
-#define PDM_COEFF_DATA 0x0A
-#define PDM_CLKG_CTRL 0x0B
-#define PDM_STS 0x0C
-
-
-/**
- * AUDIO - Registers
- * AUDIO CLOCK, TODDR, FRDDR, TDM, SPDIF, LOOPBACK, RESAMPLE,
- * POWER DETECT, SECURITY
- *
- * BASE_ADR 32'hFF642000
- */
-
-/**
- * AXG chipset
- */
-#define EE_AUDIO_CLK_GATE_EN 0x000
-#define EE_AUDIO_MCLK_A_CTRL 0x001
-#define EE_AUDIO_MCLK_B_CTRL 0x002
-#define EE_AUDIO_MCLK_C_CTRL 0x003
-#define EE_AUDIO_MCLK_D_CTRL 0x004
-#define EE_AUDIO_MCLK_E_CTRL 0x005
-#define EE_AUDIO_MCLK_F_CTRL 0x006
-#define EE_AUDIO_MST_A_SCLK_CTRL0 0x010
-#define EE_AUDIO_MST_A_SCLK_CTRL1 0x011
-#define EE_AUDIO_MST_B_SCLK_CTRL0 0x012
-#define EE_AUDIO_MST_B_SCLK_CTRL1 0x013
-#define EE_AUDIO_MST_C_SCLK_CTRL0 0x014
-#define EE_AUDIO_MST_C_SCLK_CTRL1 0x015
-#define EE_AUDIO_MST_D_SCLK_CTRL0 0x016
-#define EE_AUDIO_MST_D_SCLK_CTRL1 0x017
-#define EE_AUDIO_MST_E_SCLK_CTRL0 0x018
-#define EE_AUDIO_MST_E_SCLK_CTRL1 0x019
-#define EE_AUDIO_MST_F_SCLK_CTRL0 0x01a
-#define EE_AUDIO_MST_F_SCLK_CTRL1 0x01b
-#define EE_AUDIO_CLK_TDMIN_A_CTRL 0x020
-#define EE_AUDIO_CLK_TDMIN_B_CTRL 0x021
-#define EE_AUDIO_CLK_TDMIN_C_CTRL 0x022
-#define EE_AUDIO_CLK_TDMIN_LB_CTRL 0x023
-#define EE_AUDIO_CLK_TDMOUT_A_CTRL 0x024
-#define EE_AUDIO_CLK_TDMOUT_B_CTRL 0x025
-#define EE_AUDIO_CLK_TDMOUT_C_CTRL 0x026
-#define EE_AUDIO_CLK_SPDIFIN_CTRL 0x027
-#define EE_AUDIO_CLK_SPDIFOUT_CTRL 0x028
-#define EE_AUDIO_CLK_RESAMPLE_CTRL 0x029
-#define EE_AUDIO_CLK_LOCKER_CTRL 0x02a
-#define EE_AUDIO_CLK_PDMIN_CTRL0 0x02b
-#define EE_AUDIO_CLK_PDMIN_CTRL1 0x02c
-#define EE_AUDIO_TODDR_A_CTRL0 0x040
-#define EE_AUDIO_TODDR_A_CTRL1 0x041
-#define EE_AUDIO_TODDR_A_START_ADDR 0x042
-#define EE_AUDIO_TODDR_A_FINISH_ADDR 0x043
-#define EE_AUDIO_TODDR_A_INT_ADDR 0x044
-#define EE_AUDIO_TODDR_A_STATUS1 0x045
-#define EE_AUDIO_TODDR_A_STATUS2 0x046
-#define EE_AUDIO_TODDR_A_START_ADDRB 0x047
-#define EE_AUDIO_TODDR_A_FINISH_ADDRB 0x048
-#define EE_AUDIO_TODDR_B_CTRL0 0x050
-#define EE_AUDIO_TODDR_B_CTRL1 0x051
-#define EE_AUDIO_TODDR_B_START_ADDR 0x052
-#define EE_AUDIO_TODDR_B_FINISH_ADDR 0x053
-#define EE_AUDIO_TODDR_B_INT_ADDR 0x054
-#define EE_AUDIO_TODDR_B_STATUS1 0x055
-#define EE_AUDIO_TODDR_B_STATUS2 0x056
-#define EE_AUDIO_TODDR_B_START_ADDRB 0x057
-#define EE_AUDIO_TODDR_B_FINISH_ADDRB 0x058
-#define EE_AUDIO_TODDR_C_CTRL0 0x060
-#define EE_AUDIO_TODDR_C_CTRL1 0x061
-#define EE_AUDIO_TODDR_C_START_ADDR 0x062
-#define EE_AUDIO_TODDR_C_FINISH_ADDR 0x063
-#define EE_AUDIO_TODDR_C_INT_ADDR 0x064
-#define EE_AUDIO_TODDR_C_STATUS1 0x065
-#define EE_AUDIO_TODDR_C_STATUS2 0x066
-#define EE_AUDIO_TODDR_C_START_ADDRB 0x067
-#define EE_AUDIO_TODDR_C_FINISH_ADDRB 0x068
-#define EE_AUDIO_FRDDR_A_CTRL0 0x070
-#define EE_AUDIO_FRDDR_A_CTRL1 0x071
-#define EE_AUDIO_FRDDR_A_START_ADDR 0x072
-#define EE_AUDIO_FRDDR_A_FINISH_ADDR 0x073
-#define EE_AUDIO_FRDDR_A_INT_ADDR 0x074
-#define EE_AUDIO_FRDDR_A_STATUS1 0x075
-#define EE_AUDIO_FRDDR_A_STATUS2 0x076
-#define EE_AUDIO_FRDDR_A_START_ADDRB 0x077
-#define EE_AUDIO_FRDDR_A_FINISH_ADDRB 0x078
-#define EE_AUDIO_FRDDR_B_CTRL0 0x080
-#define EE_AUDIO_FRDDR_B_CTRL1 0x081
-#define EE_AUDIO_FRDDR_B_START_ADDR 0x082
-#define EE_AUDIO_FRDDR_B_FINISH_ADDR 0x083
-#define EE_AUDIO_FRDDR_B_INT_ADDR 0x084
-#define EE_AUDIO_FRDDR_B_STATUS1 0x085
-#define EE_AUDIO_FRDDR_B_STATUS2 0x086
-#define EE_AUDIO_FRDDR_B_START_ADDRB 0x087
-#define EE_AUDIO_FRDDR_B_FINISH_ADDRB 0x088
-#define EE_AUDIO_FRDDR_C_CTRL0 0x090
-#define EE_AUDIO_FRDDR_C_CTRL1 0x091
-#define EE_AUDIO_FRDDR_C_START_ADDR 0x092
-#define EE_AUDIO_FRDDR_C_FINISH_ADDR 0x093
-#define EE_AUDIO_FRDDR_C_INT_ADDR 0x094
-#define EE_AUDIO_FRDDR_C_STATUS1 0x095
-#define EE_AUDIO_FRDDR_C_STATUS2 0x096
-#define EE_AUDIO_FRDDR_C_START_ADDRB 0x097
-#define EE_AUDIO_FRDDR_C_FINISH_ADDRB 0x098
-#define EE_AUDIO_ARB_CTRL 0x0a0
-#define EE_AUDIO_LB_CTRL0 0x0b0
-#define EE_AUDIO_LB_CTRL1 0x0b1
-#define EE_AUDIO_TDMIN_A_CTRL 0x0c0
-#define EE_AUDIO_TDMIN_A_SWAP 0x0c1
-#define EE_AUDIO_TDMIN_A_MASK0 0x0c2
-#define EE_AUDIO_TDMIN_A_MASK1 0x0c3
-#define EE_AUDIO_TDMIN_A_MASK2 0x0c4
-#define EE_AUDIO_TDMIN_A_MASK3 0x0c5
-#define EE_AUDIO_TDMIN_A_STAT 0x0c6
-#define EE_AUDIO_TDMIN_A_MUTE_VAL 0x0c7
-#define EE_AUDIO_TDMIN_A_MUTE0 0x0c8
-#define EE_AUDIO_TDMIN_A_MUTE1 0x0c9
-#define EE_AUDIO_TDMIN_A_MUTE2 0x0ca
-#define EE_AUDIO_TDMIN_A_MUTE3 0x0cb
-#define EE_AUDIO_TDMIN_B_CTRL 0x0d0
-#define EE_AUDIO_TDMIN_B_SWAP 0x0d1
-#define EE_AUDIO_TDMIN_B_MASK0 0x0d2
-#define EE_AUDIO_TDMIN_B_MASK1 0x0d3
-#define EE_AUDIO_TDMIN_B_MASK2 0x0d4
-#define EE_AUDIO_TDMIN_B_MASK3 0x0d5
-#define EE_AUDIO_TDMIN_B_STAT 0x0d6
-#define EE_AUDIO_TDMIN_B_MUTE_VAL 0x0d7
-#define EE_AUDIO_TDMIN_B_MUTE0 0x0d8
-#define EE_AUDIO_TDMIN_B_MUTE1 0x0d9
-#define EE_AUDIO_TDMIN_B_MUTE2 0x0da
-#define EE_AUDIO_TDMIN_B_MUTE3 0x0db
-#define EE_AUDIO_TDMIN_C_CTRL 0x0e0
-#define EE_AUDIO_TDMIN_C_SWAP 0x0e1
-#define EE_AUDIO_TDMIN_C_MASK0 0x0e2
-#define EE_AUDIO_TDMIN_C_MASK1 0x0e3
-#define EE_AUDIO_TDMIN_C_MASK2 0x0e4
-#define EE_AUDIO_TDMIN_C_MASK3 0x0e5
-#define EE_AUDIO_TDMIN_C_STAT 0x0e6
-#define EE_AUDIO_TDMIN_C_MUTE_VAL 0x0e7
-#define EE_AUDIO_TDMIN_C_MUTE0 0x0e8
-#define EE_AUDIO_TDMIN_C_MUTE1 0x0e9
-#define EE_AUDIO_TDMIN_C_MUTE2 0x0ea
-#define EE_AUDIO_TDMIN_C_MUTE3 0x0eb
-#define EE_AUDIO_TDMIN_LB_CTRL 0x0f0
-#define EE_AUDIO_TDMIN_LB_SWAP 0x0f1
-#define EE_AUDIO_TDMIN_LB_MASK0 0x0f2
-#define EE_AUDIO_TDMIN_LB_MASK1 0x0f3
-#define EE_AUDIO_TDMIN_LB_MASK2 0x0f4
-#define EE_AUDIO_TDMIN_LB_MASK3 0x0f5
-#define EE_AUDIO_TDMIN_LB_STAT 0x0f6
-#define EE_AUDIO_TDMIN_LB_MUTE_VAL 0x0f7
-#define EE_AUDIO_TDMIN_LB_MUTE0 0x0f8
-#define EE_AUDIO_TDMIN_LB_MUTE1 0x0f9
-#define EE_AUDIO_TDMIN_LB_MUTE2 0x0fa
-#define EE_AUDIO_TDMIN_LB_MUTE3 0x0fb
-#define EE_AUDIO_SPDIFIN_CTRL0 0x100
-#define EE_AUDIO_SPDIFIN_CTRL1 0x101
-#define EE_AUDIO_SPDIFIN_CTRL2 0x102
-#define EE_AUDIO_SPDIFIN_CTRL3 0x103
-#define EE_AUDIO_SPDIFIN_CTRL4 0x104
-#define EE_AUDIO_SPDIFIN_CTRL5 0x105
-#define EE_AUDIO_SPDIFIN_CTRL6 0x106
-#define EE_AUDIO_SPDIFIN_STAT0 0x107
-#define EE_AUDIO_SPDIFIN_STAT1 0x108
-#define EE_AUDIO_SPDIFIN_STAT2 0x109
-#define EE_AUDIO_SPDIFIN_MUTE_VAL 0x10a
-#define EE_AUDIO_RESAMPLE_CTRL0 0x110
-#define EE_AUDIO_RESAMPLE_CTRL1 0x111
-#define EE_AUDIO_RESAMPLE_CTRL2 0x112
-#define EE_AUDIO_RESAMPLE_CTRL3 0x113
-#define EE_AUDIO_RESAMPLE_COEF0 0x114
-#define EE_AUDIO_RESAMPLE_COEF1 0x115
-#define EE_AUDIO_RESAMPLE_COEF2 0x116
-#define EE_AUDIO_RESAMPLE_COEF3 0x117
-#define EE_AUDIO_RESAMPLE_COEF4 0x118
-#define EE_AUDIO_RESAMPLE_STATUS1 0x119
-#define EE_AUDIO_SPDIFOUT_STAT 0x120
-#define EE_AUDIO_SPDIFOUT_GAIN0 0x121
-#define EE_AUDIO_SPDIFOUT_GAIN1 0x122
-#define EE_AUDIO_SPDIFOUT_CTRL0 0x123
-#define EE_AUDIO_SPDIFOUT_CTRL1 0x124
-#define EE_AUDIO_SPDIFOUT_PREAMB 0x125
-#define EE_AUDIO_SPDIFOUT_SWAP 0x126
-#define EE_AUDIO_SPDIFOUT_CHSTS0 0x127
-#define EE_AUDIO_SPDIFOUT_CHSTS1 0x128
-#define EE_AUDIO_SPDIFOUT_CHSTS2 0x129
-#define EE_AUDIO_SPDIFOUT_CHSTS3 0x12a
-#define EE_AUDIO_SPDIFOUT_CHSTS4 0x12b
-#define EE_AUDIO_SPDIFOUT_CHSTS5 0x12c
-#define EE_AUDIO_SPDIFOUT_CHSTS6 0x12d
-#define EE_AUDIO_SPDIFOUT_CHSTS7 0x12e
-#define EE_AUDIO_SPDIFOUT_CHSTS8 0x12f
-#define EE_AUDIO_SPDIFOUT_CHSTS9 0x130
-#define EE_AUDIO_SPDIFOUT_CHSTSA 0x131
-#define EE_AUDIO_SPDIFOUT_CHSTSB 0x132
-#define EE_AUDIO_SPDIFOUT_MUTE_VAL 0x133
-#define EE_AUDIO_TDMOUT_A_CTRL0 0x140
-#define EE_AUDIO_TDMOUT_A_CTRL1 0x141
-#define EE_AUDIO_TDMOUT_A_SWAP 0x142
-#define EE_AUDIO_TDMOUT_A_MASK0 0x143
-#define EE_AUDIO_TDMOUT_A_MASK1 0x144
-#define EE_AUDIO_TDMOUT_A_MASK2 0x145
-#define EE_AUDIO_TDMOUT_A_MASK3 0x146
-#define EE_AUDIO_TDMOUT_A_STAT 0x147
-#define EE_AUDIO_TDMOUT_A_GAIN0 0x148
-#define EE_AUDIO_TDMOUT_A_GAIN1 0x149
-#define EE_AUDIO_TDMOUT_A_MUTE_VAL 0x14a
-#define EE_AUDIO_TDMOUT_A_MUTE0 0x14b
-#define EE_AUDIO_TDMOUT_A_MUTE1 0x14c
-#define EE_AUDIO_TDMOUT_A_MUTE2 0x14d
-#define EE_AUDIO_TDMOUT_A_MUTE3 0x14e
-#define EE_AUDIO_TDMOUT_A_MASK_VAL 0x14f
-#define EE_AUDIO_TDMOUT_B_CTRL0 0x150
-#define EE_AUDIO_TDMOUT_B_CTRL1 0x151
-#define EE_AUDIO_TDMOUT_B_SWAP 0x152
-#define EE_AUDIO_TDMOUT_B_MASK0 0x153
-#define EE_AUDIO_TDMOUT_B_MASK1 0x154
-#define EE_AUDIO_TDMOUT_B_MASK2 0x155
-#define EE_AUDIO_TDMOUT_B_MASK3 0x156
-#define EE_AUDIO_TDMOUT_B_STAT 0x157
-#define EE_AUDIO_TDMOUT_B_GAIN0 0x158
-#define EE_AUDIO_TDMOUT_B_GAIN1 0x159
-#define EE_AUDIO_TDMOUT_B_MUTE_VAL 0x15a
-#define EE_AUDIO_TDMOUT_B_MUTE0 0x15b
-#define EE_AUDIO_TDMOUT_B_MUTE1 0x15c
-#define EE_AUDIO_TDMOUT_B_MUTE2 0x15d
-#define EE_AUDIO_TDMOUT_B_MUTE3 0x15e
-#define EE_AUDIO_TDMOUT_B_MASK_VAL 0x15f
-#define EE_AUDIO_TDMOUT_C_CTRL0 0x160
-#define EE_AUDIO_TDMOUT_C_CTRL1 0x161
-#define EE_AUDIO_TDMOUT_C_SWAP 0x162
-#define EE_AUDIO_TDMOUT_C_MASK0 0x163
-#define EE_AUDIO_TDMOUT_C_MASK1 0x164
-#define EE_AUDIO_TDMOUT_C_MASK2 0x165
-#define EE_AUDIO_TDMOUT_C_MASK3 0x166
-#define EE_AUDIO_TDMOUT_C_STAT 0x167
-#define EE_AUDIO_TDMOUT_C_GAIN0 0x168
-#define EE_AUDIO_TDMOUT_C_GAIN1 0x169
-#define EE_AUDIO_TDMOUT_C_MUTE_VAL 0x16a
-#define EE_AUDIO_TDMOUT_C_MUTE0 0x16b
-#define EE_AUDIO_TDMOUT_C_MUTE1 0x16c
-#define EE_AUDIO_TDMOUT_C_MUTE2 0x16d
-#define EE_AUDIO_TDMOUT_C_MUTE3 0x16e
-#define EE_AUDIO_TDMOUT_C_MASK_VAL 0x16f
-#define EE_AUDIO_POW_DET_CTRL0 0x180
-#define EE_AUDIO_POW_DET_TH_HI 0x181
-#define EE_AUDIO_POW_DET_TH_LO 0x182
-#define EE_AUDIO_POW_DET_VALUE 0x183
-#define EE_AUDIO_SECURITY_CTRL 0x193
-
-/**
- * AUDIO LOCKER - Registers
- *
- * BASE_ADR 32'hFF64A000
- */
-#define AUD_LOCK_EN 0x000
-#define AUD_LOCK_SW_RESET 0x001
-#define AUD_LOCK_SW_LATCH 0x002
-#define AUD_LOCK_HW_LATCH 0x003
-#define AUD_LOCK_REFCLK_SRC 0x004
-#define AUD_LOCK_REFCLK_LAT_INT 0x005
-#define AUD_LOCK_IMCLK_LAT_INT 0x006
-#define AUD_LOCK_OMCLK_LAT_INT 0x007
-#define AUD_LOCK_REFCLK_DS_INT 0x008
-#define AUD_LOCK_IMCLK_DS_INT 0x009
-#define AUD_LOCK_OMCLK_DS_INT 0x00a
-#define AUD_LOCK_INT_CLR 0x00b
-#define AUD_LOCK_GCLK_CTRL 0x00c
-#define AUD_LOCK_INT_CTRL 0x00d
-#define RO_REF2IMCLK_CNT_L 0x010
-#define RO_REF2IMCLK_CNT_H 0x011
-#define RO_REF2OMCLK_CNT_L 0x012
-#define RO_REF2OMCLK_CNT_H 0x013
-#define RO_IMCLK2REF_CNT_L 0x014
-#define RO_IMCLK2REF_CNT_H 0x015
-#define RO_OMCLK2REF_CNT_L 0x016
-#define RO_OMCLK2REF_CNT_H 0x017
-#define RO_REFCLK_PKG_CNT 0x018
-#define RO_IMCLK_PKG_CNT 0x019
-#define RO_OMCLK_PKG_CNT 0x01a
-#define RO_AUD_LOCK_INT_STATUS 0x01b
-
-/**
- * G12A chipset, base axg chipset, new registers
- */
-
-/* pdm mute value, mute channel ctrl in PDM_CTRL */
-#define PDM_MUTE_VALUE 0x00d
-
-/* clk pad */
-#define EE_AUDIO_MST_PAD_CTRL0 0x007
-#define EE_AUDIO_MST_PAD_CTRL1 0x008
-#define EE_AUDIO_SW_RESET 0x009
-/* spdifout_b clk*/
-#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL 0x02d
-
-/* toddr, frddr int address */
-#define EE_AUDIO_TODDR_A_INIT_ADDR 0x049
-#define EE_AUDIO_TODDR_B_INIT_ADDR 0x059
-#define EE_AUDIO_TODDR_C_INIT_ADDR 0x069
-#define EE_AUDIO_FRDDR_A_INIT_ADDR 0x079
-#define EE_AUDIO_FRDDR_B_INIT_ADDR 0x089
-#define EE_AUDIO_FRDDR_C_INIT_ADDR 0x099
-/* spdif_b registers */
-#define EE_AUDIO_SPDIFOUT_B_STAT 0x1a0
-#define EE_AUDIO_SPDIFOUT_B_GAIN0 0x1a1
-#define EE_AUDIO_SPDIFOUT_B_GAIN1 0x1a2
-#define EE_AUDIO_SPDIFOUT_B_CTRL0 0x1a3
-#define EE_AUDIO_SPDIFOUT_B_CTRL1 0x1a4
-#define EE_AUDIO_SPDIFOUT_B_PREAMB 0x1a5
-#define EE_AUDIO_SPDIFOUT_B_SWAP 0x1a6
-#define EE_AUDIO_SPDIFOUT_B_CHSTS0 0x1a7
-#define EE_AUDIO_SPDIFOUT_B_CHSTS1 0x1a8
-#define EE_AUDIO_SPDIFOUT_B_CHSTS2 0x1a9
-#define EE_AUDIO_SPDIFOUT_B_CHSTS3 0x1aa
-#define EE_AUDIO_SPDIFOUT_B_CHSTS4 0x1ab
-#define EE_AUDIO_SPDIFOUT_B_CHSTS5 0x1ac
-#define EE_AUDIO_SPDIFOUT_B_CHSTS6 0x1ad
-#define EE_AUDIO_SPDIFOUT_B_CHSTS7 0x1ae
-#define EE_AUDIO_SPDIFOUT_B_CHSTS8 0x1af
-#define EE_AUDIO_SPDIFOUT_B_CHSTS9 0x1b0
-#define EE_AUDIO_SPDIFOUT_B_CHSTSA 0x1b1
-#define EE_AUDIO_SPDIFOUT_B_CHSTSB 0x1b2
-#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL 0x1b3
-
-/* data id */
-#define EE_AUDIO_DAT_ID0 0x0b2
-#define EE_AUDIO_DAT_ID1 0x0b3
-/* lb id */
-#define EE_AUDIO_LB_ID0 0x0b4
-#define EE_AUDIO_LB_ID1 0x0b5
-#define EE_AUDIO_LB_STS 0x0b6
-
-/* TORAM Registers */
-#define EE_AUDIO_TORAM_CTRL0 0x1c0
-#define EE_AUDIO_TORAM_CTRL1 0x1c1
-#define EE_AUDIO_TORAM_START_ADDR 0x1c2
-#define EE_AUDIO_TORAM_FINISH_ADDR 0x1c3
-#define EE_AUDIO_TORAM_INT_ADDR 0x1c4
-#define EE_AUDIO_TORAM_STATUS1 0x1c5
-#define EE_AUDIO_TORAM_STATUS2 0x1c6
-#define EE_AUDIO_TORAM_INIT_ADDR 0x1c7
-/* TOACODEC Registers */
-#define EE_AUDIO_TOACODEC_CTRL0 0x1d0
-/* TOHDMITX Registers */
-#define EE_AUDIO_TOHDMITX_CTRL0 0x1d1
-
-/* acodec reset */
-#define EE_RESET1 0x002
-
-/* EQ DRC
- * check BASE_ADR according to chipset
- */
-#define AED_EQ_CH1_COEF00 0x00
-#define AED_EQ_CH1_COEF01 0x01
-#define AED_EQ_CH1_COEF02 0x02
-#define AED_EQ_CH1_COEF03 0x03
-#define AED_EQ_CH1_COEF04 0x04
-#define AED_EQ_CH1_COEF10 0x05
-#define AED_EQ_CH1_COEF11 0x06
-#define AED_EQ_CH1_COEF12 0x07
-#define AED_EQ_CH1_COEF13 0x08
-#define AED_EQ_CH1_COEF14 0x09
-#define AED_EQ_CH1_COEF20 0x0a
-#define AED_EQ_CH1_COEF21 0x0b
-#define AED_EQ_CH1_COEF22 0x0c
-#define AED_EQ_CH1_COEF23 0x0d
-#define AED_EQ_CH1_COEF24 0x0e
-#define AED_EQ_CH1_COEF30 0x0f
-#define AED_EQ_CH1_COEF31 0x10
-#define AED_EQ_CH1_COEF32 0x11
-#define AED_EQ_CH1_COEF33 0x12
-#define AED_EQ_CH1_COEF34 0x13
-#define AED_EQ_CH1_COEF40 0x14
-#define AED_EQ_CH1_COEF41 0x15
-#define AED_EQ_CH1_COEF42 0x16
-#define AED_EQ_CH1_COEF43 0x17
-#define AED_EQ_CH1_COEF44 0x18
-#define AED_EQ_CH1_COEF50 0x19
-#define AED_EQ_CH1_COEF51 0x1a
-#define AED_EQ_CH1_COEF52 0x1b
-#define AED_EQ_CH1_COEF53 0x1c
-#define AED_EQ_CH1_COEF54 0x1d
-#define AED_EQ_CH1_COEF60 0x1e
-#define AED_EQ_CH1_COEF61 0x1f
-#define AED_EQ_CH1_COEF62 0x20
-#define AED_EQ_CH1_COEF63 0x21
-#define AED_EQ_CH1_COEF64 0x22
-#define AED_EQ_CH1_COEF70 0x23
-#define AED_EQ_CH1_COEF71 0x24
-#define AED_EQ_CH1_COEF72 0x25
-#define AED_EQ_CH1_COEF73 0x26
-#define AED_EQ_CH1_COEF74 0x27
-#define AED_EQ_CH1_COEF80 0x28
-#define AED_EQ_CH1_COEF81 0x29
-#define AED_EQ_CH1_COEF82 0x2a
-#define AED_EQ_CH1_COEF83 0x2b
-#define AED_EQ_CH1_COEF84 0x2c
-#define AED_EQ_CH1_COEF90 0x2d
-#define AED_EQ_CH1_COEF91 0x2e
-#define AED_EQ_CH1_COEF92 0x2f
-#define AED_EQ_CH1_COEF93 0x30
-#define AED_EQ_CH1_COEF94 0x31
-#define AED_EQ_CH2_COEF00 0x32
-#define AED_EQ_CH2_COEF01 0x33
-#define AED_EQ_CH2_COEF02 0x34
-#define AED_EQ_CH2_COEF03 0x35
-#define AED_EQ_CH2_COEF04 0x36
-#define AED_EQ_CH2_COEF10 0x37
-#define AED_EQ_CH2_COEF11 0x38
-#define AED_EQ_CH2_COEF12 0x39
-#define AED_EQ_CH2_COEF13 0x3a
-#define AED_EQ_CH2_COEF14 0x3b
-#define AED_EQ_CH2_COEF20 0x3c
-#define AED_EQ_CH2_COEF21 0x3d
-#define AED_EQ_CH2_COEF22 0x3e
-#define AED_EQ_CH2_COEF23 0x3f
-#define AED_EQ_CH2_COEF24 0x40
-#define AED_EQ_CH2_COEF30 0x41
-#define AED_EQ_CH2_COEF31 0x42
-#define AED_EQ_CH2_COEF32 0x43
-#define AED_EQ_CH2_COEF33 0x44
-#define AED_EQ_CH2_COEF34 0x45
-#define AED_EQ_CH2_COEF40 0x46
-#define AED_EQ_CH2_COEF41 0x47
-#define AED_EQ_CH2_COEF42 0x48
-#define AED_EQ_CH2_COEF43 0x49
-#define AED_EQ_CH2_COEF44 0x4a
-#define AED_EQ_CH2_COEF50 0x4b
-#define AED_EQ_CH2_COEF51 0x4c
-#define AED_EQ_CH2_COEF52 0x4d
-#define AED_EQ_CH2_COEF53 0x4e
-#define AED_EQ_CH2_COEF54 0x4f
-#define AED_EQ_CH2_COEF60 0x50
-#define AED_EQ_CH2_COEF61 0x51
-#define AED_EQ_CH2_COEF62 0x52
-#define AED_EQ_CH2_COEF63 0x53
-#define AED_EQ_CH2_COEF64 0x54
-#define AED_EQ_CH2_COEF70 0x55
-#define AED_EQ_CH2_COEF71 0x56
-#define AED_EQ_CH2_COEF72 0x57
-#define AED_EQ_CH2_COEF73 0x58
-#define AED_EQ_CH2_COEF74 0x59
-#define AED_EQ_CH2_COEF80 0x5a
-#define AED_EQ_CH2_COEF81 0x5b
-#define AED_EQ_CH2_COEF82 0x5c
-#define AED_EQ_CH2_COEF83 0x5d
-#define AED_EQ_CH2_COEF84 0x5e
-#define AED_EQ_CH2_COEF90 0x5f
-#define AED_EQ_CH2_COEF91 0x60
-#define AED_EQ_CH2_COEF92 0x61
-#define AED_EQ_CH2_COEF93 0x62
-#define AED_EQ_CH2_COEF94 0x63
-#define AED_EQ_EN 0x64
-#define AED_EQ_VOLUME 0x65
-#define AED_EQ_VOLUME_SLEW_CNT 0x66
-#define AED_MUTE 0x67
-#define AED_DRC_EN 0x68
-#define AED_DRC_AE 0x69
-#define AED_DRC_AA 0x6a
-#define AED_DRC_AD 0x6b
-#define AED_DRC_AE_1M 0x6c
-#define AED_DRC_AA_1M 0x6d
-#define AED_DRC_AD_1M 0x6e
-#define AED_DRC_OFFSET0 0x6f
-#define AED_DRC_OFFSET1 0x70
-#define AED_DRC_THD0 0x71
-#define AED_DRC_THD1 0x72
-#define AED_DRC_K0 0x73
-#define AED_DRC_K1 0x74
-#define AED_CLIP_THD 0x75
-#define AED_NG_THD0 0x76
-#define AED_NG_THD1 0x77
-#define AED_NG_CNT_THD 0x78
-#define AED_NG_CTL 0x79
-#define AED_ED_CTL 0x7a
-#define AED_DEBUG0 0x7b
-#define AED_DEBUG1 0x7c
-#define AED_DEBUG2 0x7d
-#define AED_DEBUG3 0x7e
-#define AED_DEBUG4 0x7f
-#define AED_DEBUG5 0x80
-#define AED_DEBUG6 0x81
-#define AED_DRC_AA_H 0x82
-#define AED_DRC_AD_H 0x83
-#define AED_DRC_AA_1M_H 0x84
-#define AED_DRC_AD_1M_H 0x85
-#define AED_NG_CNT 0x86
-#define AED_NG_STEP 0x87
-#define AED_TOP_CTL 0x88
-#define AED_TOP_REQ_CTL 0x89
-
-
-#define AUD_ADDR_OFFSET(addr) ((addr) << 2)
-
enum clk_sel {
MASTER_A,
MASTER_B,
SLAVE_J
};
+#define AUD_ADDR_OFFSET(addr) ((addr) << 2)
+
+/*
+ * PDM - Registers
+ */
+#define PDM_CTRL 0x00
+#define PDM_HCIC_CTRL1 0x01
+#define PDM_HCIC_CTRL2 0x02
+#define PDM_F1_CTRL 0x03
+#define PDM_F2_CTRL 0x04
+#define PDM_F3_CTRL 0x05
+#define PDM_HPF_CTRL 0x06
+#define PDM_CHAN_CTRL 0x07
+#define PDM_CHAN_CTRL1 0x08
+#define PDM_COEFF_ADDR 0x09
+#define PDM_COEFF_DATA 0x0A
+#define PDM_CLKG_CTRL 0x0B
+#define PDM_STS 0x0C
+#define PDM_MUTE_VALUE 0x0D
+#define PDM_MASK_NUM 0x0E
+
+/*
+ * AUDIO CLOCK, MST PAD,
+ */
+#define EE_AUDIO_CLK_GATE_EN0 0x000
+#define EE_AUDIO_CLK_GATE_EN1 0x001
+#define EE_AUDIO_MCLK_A_CTRL(offset) (0x001 + offset)
+#define EE_AUDIO_MCLK_B_CTRL(offset) (0x002 + offset)
+#define EE_AUDIO_MCLK_C_CTRL(offset) (0x003 + offset)
+#define EE_AUDIO_MCLK_D_CTRL(offset) (0x004 + offset)
+#define EE_AUDIO_MCLK_E_CTRL(offset) (0x005 + offset)
+#define EE_AUDIO_MCLK_F_CTRL(offset) (0x006 + offset)
+#define EE_AUDIO_MST_PAD_CTRL0(offset) (0x007 + offset)
+#define EE_AUDIO_MST_PAD_CTRL1(offset) (0x008 + offset)
+#define EE_AUDIO_SW_RESET0(offset) (0x009 + offset)
+#define EE_AUDIO_SW_RESET1 0x00b
+#define EE_AUDIO_CLK81_CTRL 0x00c
+#define EE_AUDIO_CLK81_EN 0x00d
+
+
+#define EE_AUDIO_MST_A_SCLK_CTRL0 0x010
+#define EE_AUDIO_MST_A_SCLK_CTRL1 0x011
+#define EE_AUDIO_MST_B_SCLK_CTRL0 0x012
+#define EE_AUDIO_MST_B_SCLK_CTRL1 0x013
+#define EE_AUDIO_MST_C_SCLK_CTRL0 0x014
+#define EE_AUDIO_MST_C_SCLK_CTRL1 0x015
+#define EE_AUDIO_MST_D_SCLK_CTRL0 0x016
+#define EE_AUDIO_MST_D_SCLK_CTRL1 0x017
+#define EE_AUDIO_MST_E_SCLK_CTRL0 0x018
+#define EE_AUDIO_MST_E_SCLK_CTRL1 0x019
+#define EE_AUDIO_MST_F_SCLK_CTRL0 0x01a
+#define EE_AUDIO_MST_F_SCLK_CTRL1 0x01b
+
+#define EE_AUDIO_CLK_TDMIN_A_CTRL 0x020
+#define EE_AUDIO_CLK_TDMIN_B_CTRL 0x021
+#define EE_AUDIO_CLK_TDMIN_C_CTRL 0x022
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL 0x023
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL 0x024
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL 0x025
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL 0x026
+#define EE_AUDIO_CLK_SPDIFIN_CTRL 0x027
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL 0x028
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL 0x029
+#define EE_AUDIO_CLK_LOCKER_CTRL 0x02a
+#define EE_AUDIO_CLK_PDMIN_CTRL0 0x02b
+#define EE_AUDIO_CLK_PDMIN_CTRL1 0x02c
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL 0x02d
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL 0x02e
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL 0x02f
+#define EE_AUDIO_CLK_EQDRC_CTRL0 0x030
+#define EE_AUDIO_VAD_CLK_CTRL 0x031
+
+/*
+ * AUDIO TODDR
+ */
+#define EE_AUDIO_TODDR_A_CTRL0 0x040
+#define EE_AUDIO_TODDR_A_CTRL1 0x041
+#define EE_AUDIO_TODDR_A_START_ADDR 0x042
+#define EE_AUDIO_TODDR_A_FINISH_ADDR 0x043
+#define EE_AUDIO_TODDR_A_INT_ADDR 0x044
+#define EE_AUDIO_TODDR_A_STATUS1 0x045
+#define EE_AUDIO_TODDR_A_STATUS2 0x046
+#define EE_AUDIO_TODDR_A_START_ADDRB 0x047
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB 0x048
+#define EE_AUDIO_TODDR_A_INIT_ADDR 0x049
+#define EE_AUDIO_TODDR_A_CTRL2 0x04a
+
+#define EE_AUDIO_TODDR_B_CTRL0 0x050
+#define EE_AUDIO_TODDR_B_CTRL1 0x051
+#define EE_AUDIO_TODDR_B_START_ADDR 0x052
+#define EE_AUDIO_TODDR_B_FINISH_ADDR 0x053
+#define EE_AUDIO_TODDR_B_INT_ADDR 0x054
+#define EE_AUDIO_TODDR_B_STATUS1 0x055
+#define EE_AUDIO_TODDR_B_STATUS2 0x056
+#define EE_AUDIO_TODDR_B_START_ADDRB 0x057
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB 0x058
+#define EE_AUDIO_TODDR_B_INIT_ADDR 0x059
+#define EE_AUDIO_TODDR_B_CTRL2 0x05a
+
+#define EE_AUDIO_TODDR_C_CTRL0 0x060
+#define EE_AUDIO_TODDR_C_CTRL1 0x061
+#define EE_AUDIO_TODDR_C_START_ADDR 0x062
+#define EE_AUDIO_TODDR_C_FINISH_ADDR 0x063
+#define EE_AUDIO_TODDR_C_INT_ADDR 0x064
+#define EE_AUDIO_TODDR_C_STATUS1 0x065
+#define EE_AUDIO_TODDR_C_STATUS2 0x066
+#define EE_AUDIO_TODDR_C_START_ADDRB 0x067
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB 0x068
+#define EE_AUDIO_TODDR_C_INIT_ADDR 0x069
+#define EE_AUDIO_TODDR_C_CTRL2 0x06a
+
+/*
+ * AUDIO FRDDR
+ */
+#define EE_AUDIO_FRDDR_A_CTRL0 0x070
+#define EE_AUDIO_FRDDR_A_CTRL1 0x071
+#define EE_AUDIO_FRDDR_A_START_ADDR 0x072
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR 0x073
+#define EE_AUDIO_FRDDR_A_INT_ADDR 0x074
+#define EE_AUDIO_FRDDR_A_STATUS1 0x075
+#define EE_AUDIO_FRDDR_A_STATUS2 0x076
+#define EE_AUDIO_FRDDR_A_START_ADDRB 0x077
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB 0x078
+#define EE_AUDIO_FRDDR_A_INIT_ADDR 0x079
+#define EE_AUDIO_FRDDR_A_CTRL2 0x07a
+
+#define EE_AUDIO_FRDDR_B_CTRL0 0x080
+#define EE_AUDIO_FRDDR_B_CTRL1 0x081
+#define EE_AUDIO_FRDDR_B_START_ADDR 0x082
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR 0x083
+#define EE_AUDIO_FRDDR_B_INT_ADDR 0x084
+#define EE_AUDIO_FRDDR_B_STATUS1 0x085
+#define EE_AUDIO_FRDDR_B_STATUS2 0x086
+#define EE_AUDIO_FRDDR_B_START_ADDRB 0x087
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB 0x088
+#define EE_AUDIO_FRDDR_B_INIT_ADDR 0x089
+#define EE_AUDIO_FRDDR_B_CTRL2 0x08a
+
+#define EE_AUDIO_FRDDR_C_CTRL0 0x090
+#define EE_AUDIO_FRDDR_C_CTRL1 0x091
+#define EE_AUDIO_FRDDR_C_START_ADDR 0x092
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR 0x093
+#define EE_AUDIO_FRDDR_C_INT_ADDR 0x094
+#define EE_AUDIO_FRDDR_C_STATUS1 0x095
+#define EE_AUDIO_FRDDR_C_STATUS2 0x096
+#define EE_AUDIO_FRDDR_C_START_ADDRB 0x097
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB 0x098
+#define EE_AUDIO_FRDDR_C_INIT_ADDR 0x099
+#define EE_AUDIO_FRDDR_C_CTRL2 0x09a
+
+/*
+ * AUDIO ARB,
+ */
+#define EE_AUDIO_ARB_CTRL 0x0a0
+
+/*
+ * AUDIO TDM
+ */
+#define EE_AUDIO_LB_CTRL0 0x0b0
+#define EE_AUDIO_LB_CTRL1 0x0b1
+#define EE_AUDIO_DAT_ID0 0x0b2
+#define EE_AUDIO_DAT_ID1 0x0b3
+#define EE_AUDIO_LB_ID0 0x0b4
+#define EE_AUDIO_LB_ID1 0x0b5
+#define EE_AUDIO_LB_STS 0x0b6
+
+#define EE_AUDIO_TDMIN_A_CTRL 0x0c0
+#define EE_AUDIO_TDMIN_A_SWAP 0x0c1
+#define EE_AUDIO_TDMIN_A_MASK0 0x0c2
+#define EE_AUDIO_TDMIN_A_MASK1 0x0c3
+#define EE_AUDIO_TDMIN_A_MASK2 0x0c4
+#define EE_AUDIO_TDMIN_A_MASK3 0x0c5
+#define EE_AUDIO_TDMIN_A_STAT 0x0c6
+#define EE_AUDIO_TDMIN_A_MUTE_VAL 0x0c7
+#define EE_AUDIO_TDMIN_A_MUTE0 0x0c8
+#define EE_AUDIO_TDMIN_A_MUTE1 0x0c9
+#define EE_AUDIO_TDMIN_A_MUTE2 0x0ca
+#define EE_AUDIO_TDMIN_A_MUTE3 0x0cb
+
+#define EE_AUDIO_TDMIN_B_CTRL 0x0d0
+#define EE_AUDIO_TDMIN_B_SWAP 0x0d1
+#define EE_AUDIO_TDMIN_B_MASK0 0x0d2
+#define EE_AUDIO_TDMIN_B_MASK1 0x0d3
+#define EE_AUDIO_TDMIN_B_MASK2 0x0d4
+#define EE_AUDIO_TDMIN_B_MASK3 0x0d5
+#define EE_AUDIO_TDMIN_B_STAT 0x0d6
+#define EE_AUDIO_TDMIN_B_MUTE_VAL 0x0d7
+#define EE_AUDIO_TDMIN_B_MUTE0 0x0d8
+#define EE_AUDIO_TDMIN_B_MUTE1 0x0d9
+#define EE_AUDIO_TDMIN_B_MUTE2 0x0da
+#define EE_AUDIO_TDMIN_B_MUTE3 0x0db
+
+#define EE_AUDIO_TDMIN_C_CTRL 0x0e0
+#define EE_AUDIO_TDMIN_C_SWAP 0x0e1
+#define EE_AUDIO_TDMIN_C_MASK0 0x0e2
+#define EE_AUDIO_TDMIN_C_MASK1 0x0e3
+#define EE_AUDIO_TDMIN_C_MASK2 0x0e4
+#define EE_AUDIO_TDMIN_C_MASK3 0x0e5
+#define EE_AUDIO_TDMIN_C_STAT 0x0e6
+#define EE_AUDIO_TDMIN_C_MUTE_VAL 0x0e7
+#define EE_AUDIO_TDMIN_C_MUTE0 0x0e8
+#define EE_AUDIO_TDMIN_C_MUTE1 0x0e9
+#define EE_AUDIO_TDMIN_C_MUTE2 0x0ea
+#define EE_AUDIO_TDMIN_C_MUTE3 0x0eb
+
+#define EE_AUDIO_TDMIN_LB_CTRL 0x0f0
+#define EE_AUDIO_TDMIN_LB_SWAP 0x0f1
+#define EE_AUDIO_TDMIN_LB_MASK0 0x0f2
+#define EE_AUDIO_TDMIN_LB_MASK1 0x0f3
+#define EE_AUDIO_TDMIN_LB_MASK2 0x0f4
+#define EE_AUDIO_TDMIN_LB_MASK3 0x0f5
+#define EE_AUDIO_TDMIN_LB_STAT 0x0f6
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL 0x0f7
+#define EE_AUDIO_TDMIN_LB_MUTE0 0x0f8
+#define EE_AUDIO_TDMIN_LB_MUTE1 0x0f9
+#define EE_AUDIO_TDMIN_LB_MUTE2 0x0fa
+#define EE_AUDIO_TDMIN_LB_MUTE3 0x0fb
+
+/*
+ * AUDIO OUTPUT
+ */
+#define EE_AUDIO_SPDIFIN_CTRL0 0x100
+#define EE_AUDIO_SPDIFIN_CTRL1 0x101
+#define EE_AUDIO_SPDIFIN_CTRL2 0x102
+#define EE_AUDIO_SPDIFIN_CTRL3 0x103
+#define EE_AUDIO_SPDIFIN_CTRL4 0x104
+#define EE_AUDIO_SPDIFIN_CTRL5 0x105
+#define EE_AUDIO_SPDIFIN_CTRL6 0x106
+#define EE_AUDIO_SPDIFIN_STAT0 0x107
+#define EE_AUDIO_SPDIFIN_STAT1 0x108
+#define EE_AUDIO_SPDIFIN_STAT2 0x109
+#define EE_AUDIO_SPDIFIN_MUTE_VAL 0x10a
+
+#define EE_AUDIO_RESAMPLE_CTRL0 0x110
+#define EE_AUDIO_RESAMPLE_CTRL1 0x111
+#define EE_AUDIO_RESAMPLE_CTRL2 0x112
+#define EE_AUDIO_RESAMPLE_CTRL3 0x113
+#define EE_AUDIO_RESAMPLE_COEF0 0x114
+#define EE_AUDIO_RESAMPLE_COEF1 0x115
+#define EE_AUDIO_RESAMPLE_COEF2 0x116
+#define EE_AUDIO_RESAMPLE_COEF3 0x117
+#define EE_AUDIO_RESAMPLE_COEF4 0x118
+#define EE_AUDIO_RESAMPLE_STATUS1 0x119
+
+#define EE_AUDIO_SPDIFOUT_STAT 0x120
+#define EE_AUDIO_SPDIFOUT_GAIN0 0x121
+#define EE_AUDIO_SPDIFOUT_GAIN1 0x122
+#define EE_AUDIO_SPDIFOUT_CTRL0 0x123
+#define EE_AUDIO_SPDIFOUT_CTRL1 0x124
+#define EE_AUDIO_SPDIFOUT_PREAMB 0x125
+#define EE_AUDIO_SPDIFOUT_SWAP 0x126
+#define EE_AUDIO_SPDIFOUT_CHSTS0 0x127
+#define EE_AUDIO_SPDIFOUT_CHSTS1 0x128
+#define EE_AUDIO_SPDIFOUT_CHSTS2 0x129
+#define EE_AUDIO_SPDIFOUT_CHSTS3 0x12a
+#define EE_AUDIO_SPDIFOUT_CHSTS4 0x12b
+#define EE_AUDIO_SPDIFOUT_CHSTS5 0x12c
+#define EE_AUDIO_SPDIFOUT_CHSTS6 0x12d
+#define EE_AUDIO_SPDIFOUT_CHSTS7 0x12e
+#define EE_AUDIO_SPDIFOUT_CHSTS8 0x12f
+#define EE_AUDIO_SPDIFOUT_CHSTS9 0x130
+#define EE_AUDIO_SPDIFOUT_CHSTSA 0x131
+#define EE_AUDIO_SPDIFOUT_CHSTSB 0x132
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL 0x133
+
+#define EE_AUDIO_TDMOUT_A_CTRL0 0x140
+#define EE_AUDIO_TDMOUT_A_CTRL1 0x141
+#define EE_AUDIO_TDMOUT_A_SWAP 0x142
+#define EE_AUDIO_TDMOUT_A_MASK0 0x143
+#define EE_AUDIO_TDMOUT_A_MASK1 0x144
+#define EE_AUDIO_TDMOUT_A_MASK2 0x145
+#define EE_AUDIO_TDMOUT_A_MASK3 0x146
+#define EE_AUDIO_TDMOUT_A_STAT 0x147
+#define EE_AUDIO_TDMOUT_A_GAIN0 0x148
+#define EE_AUDIO_TDMOUT_A_GAIN1 0x149
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL 0x14a
+#define EE_AUDIO_TDMOUT_A_MUTE0 0x14b
+#define EE_AUDIO_TDMOUT_A_MUTE1 0x14c
+#define EE_AUDIO_TDMOUT_A_MUTE2 0x14d
+#define EE_AUDIO_TDMOUT_A_MUTE3 0x14e
+#define EE_AUDIO_TDMOUT_A_MASK_VAL 0x14f
+
+#define EE_AUDIO_TDMOUT_B_CTRL0 0x150
+#define EE_AUDIO_TDMOUT_B_CTRL1 0x151
+#define EE_AUDIO_TDMOUT_B_SWAP 0x152
+#define EE_AUDIO_TDMOUT_B_MASK0 0x153
+#define EE_AUDIO_TDMOUT_B_MASK1 0x154
+#define EE_AUDIO_TDMOUT_B_MASK2 0x155
+#define EE_AUDIO_TDMOUT_B_MASK3 0x156
+#define EE_AUDIO_TDMOUT_B_STAT 0x157
+#define EE_AUDIO_TDMOUT_B_GAIN0 0x158
+#define EE_AUDIO_TDMOUT_B_GAIN1 0x159
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL 0x15a
+#define EE_AUDIO_TDMOUT_B_MUTE0 0x15b
+#define EE_AUDIO_TDMOUT_B_MUTE1 0x15c
+#define EE_AUDIO_TDMOUT_B_MUTE2 0x15d
+#define EE_AUDIO_TDMOUT_B_MUTE3 0x15e
+#define EE_AUDIO_TDMOUT_B_MASK_VAL 0x15f
+
+#define EE_AUDIO_TDMOUT_C_CTRL0 0x160
+#define EE_AUDIO_TDMOUT_C_CTRL1 0x161
+#define EE_AUDIO_TDMOUT_C_SWAP 0x162
+#define EE_AUDIO_TDMOUT_C_MASK0 0x163
+#define EE_AUDIO_TDMOUT_C_MASK1 0x164
+#define EE_AUDIO_TDMOUT_C_MASK2 0x165
+#define EE_AUDIO_TDMOUT_C_MASK3 0x166
+#define EE_AUDIO_TDMOUT_C_STAT 0x167
+#define EE_AUDIO_TDMOUT_C_GAIN0 0x168
+#define EE_AUDIO_TDMOUT_C_GAIN1 0x169
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL 0x16a
+#define EE_AUDIO_TDMOUT_C_MUTE0 0x16b
+#define EE_AUDIO_TDMOUT_C_MUTE1 0x16c
+#define EE_AUDIO_TDMOUT_C_MUTE2 0x16d
+#define EE_AUDIO_TDMOUT_C_MUTE3 0x16e
+#define EE_AUDIO_TDMOUT_C_MASK_VAL 0x16f
+
+/*
+ * AUDIO POWER DETECT
+ */
+#define EE_AUDIO_POW_DET_CTRL0 0x180
+#define EE_AUDIO_POW_DET_TH_HI 0x181
+#define EE_AUDIO_POW_DET_TH_LO 0x182
+#define EE_AUDIO_POW_DET_VALUE 0x183
+#define EE_AUDIO_SECURITY_CTRL 0x193
+
+/*
+ * AUDIO SPDIF_B
+ */
+#define EE_AUDIO_SPDIFOUT_B_STAT 0x1a0
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 0x1a1
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 0x1a2
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 0x1a3
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 0x1a4
+#define EE_AUDIO_SPDIFOUT_B_PREAMB 0x1a5
+#define EE_AUDIO_SPDIFOUT_B_SWAP 0x1a6
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 0x1a7
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 0x1a8
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 0x1a9
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 0x1aa
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 0x1ab
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 0x1ac
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 0x1ad
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 0x1ae
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 0x1af
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 0x1b0
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA 0x1b1
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB 0x1b2
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL 0x1b3
+
+/*
+ * AUDIO LOCKER
+ */
+#define EE_AUDIO_TORAM_CTRL0 0x1c0
+#define EE_AUDIO_TORAM_CTRL1 0x1c1
+#define EE_AUDIO_TORAM_START_ADDR 0x1c2
+#define EE_AUDIO_TORAM_FINISH_ADDR 0x1c3
+#define EE_AUDIO_TORAM_INT_ADDR 0x1c4
+#define EE_AUDIO_TORAM_STATUS1 0x1c5
+#define EE_AUDIO_TORAM_STATUS2 0x1c6
+#define EE_AUDIO_TORAM_INIT_ADDR 0x1c7
+
+/*
+ * HIU, AUDIO CODEC RESET
+ */
+#define EE_RESET1 0x002
+
+/*
+ * AUDIO MUX CONTROLS
+ */
+#define EE_AUDIO_TOACODEC_CTRL0 0x1d0
+#define EE_AUDIO_TOHDMITX_CTRL0 0x1d1
+#define EE_AUDIO_TOVAD_CTRL0 0x1d2
+#define EE_AUDIO_FRATV_CTRL0 0x1d3
+
+#define EE_AUDIO_RESAMPLEB_CTRL0 0x1e0
+#define EE_AUDIO_RESAMPLEB_CTRL1 0x1e1
+#define EE_AUDIO_RESAMPLEB_CTRL2 0x1e2
+#define EE_AUDIO_RESAMPLEB_CTRL3 0x1e3
+#define EE_AUDIO_RESAMPLEB_COEF0 0x1e4
+#define EE_AUDIO_RESAMPLEB_COEF1 0x1e5
+#define EE_AUDIO_RESAMPLEB_COEF2 0x1e6
+#define EE_AUDIO_RESAMPLEB_COEF3 0x1e7
+#define EE_AUDIO_RESAMPLEB_COEF4 0x1e8
+#define EE_AUDIO_RESAMPLEB_STATUS1 0x1e9
+
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 0x1f0
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 0x1f1
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 0x1f6
+#define EE_AUDIO_SPDIFIN_LB_STAT0 0x1f7
+#define EE_AUDIO_SPDIFIN_LB_STAT1 0x1f8
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL 0x1fa
+
+#define EE_AUDIO_FRHDMIRX_CTRL0 0x200
+#define EE_AUDIO_FRHDMIRX_CTRL1 0x201
+#define EE_AUDIO_FRHDMIRX_CTRL2 0x202
+#define EE_AUDIO_FRHDMIRX_CTRL3 0x203
+#define EE_AUDIO_FRHDMIRX_CTRL4 0x204
+#define EE_AUDIO_FRHDMIRX_CTRL5 0x205
+#define EE_AUDIO_FRHDMIRX_STAT0 0x20a
+#define EE_AUDIO_FRHDMIRX_STAT1 0x20b
+
+#define EE_AUDIO_TODDR_D_CTRL0 0x210
+#define EE_AUDIO_TODDR_D_CTRL1 0x211
+#define EE_AUDIO_TODDR_D_START_ADDR 0x212
+#define EE_AUDIO_TODDR_D_FINISH_ADDR 0x213
+#define EE_AUDIO_TODDR_D_INT_ADDR 0x214
+#define EE_AUDIO_TODDR_D_STATUS1 0x215
+#define EE_AUDIO_TODDR_D_STATUS2 0x216
+#define EE_AUDIO_TODDR_D_START_ADDRB 0x217
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB 0x218
+#define EE_AUDIO_TODDR_D_INIT_ADDR 0x219
+#define EE_AUDIO_TODDR_D_CTRL2 0x21a
+
+#define EE_AUDIO_FRDDR_D_CTRL0 0x220
+#define EE_AUDIO_FRDDR_D_CTRL1 0x221
+#define EE_AUDIO_FRDDR_D_START_ADDR 0x222
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR 0x223
+#define EE_AUDIO_FRDDR_D_INT_ADDR 0x224
+#define EE_AUDIO_FRDDR_D_STATUS1 0x225
+#define EE_AUDIO_FRDDR_D_STATUS2 0x226
+#define EE_AUDIO_FRDDR_D_START_ADDRB 0x227
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB 0x228
+#define EE_AUDIO_FRDDR_D_INIT_ADDR 0x229
+#define EE_AUDIO_FRDDR_D_CTRL2 0x22a
+
+#define EE_AUDIO_LB_B_CTRL0 0x230
+#define EE_AUDIO_LB_B_CTRL1 0x231
+#define EE_AUDIO_LB_B_CTRL2 0x232
+#define EE_AUDIO_LB_B_CTRL3 0x233
+#define EE_AUDIO_LB_B_DAT_CH_ID0 0x234
+#define EE_AUDIO_LB_B_DAT_CH_ID1 0x235
+#define EE_AUDIO_LB_B_DAT_CH_ID2 0x236
+#define EE_AUDIO_LB_B_DAT_CH_ID3 0x237
+#define EE_AUDIO_LB_B_LB_CH_ID0 0x238
+#define EE_AUDIO_LB_B_LB_CH_ID1 0x239
+#define EE_AUDIO_LB_B_LB_CH_ID2 0x23a
+#define EE_AUDIO_LB_B_LB_CH_ID3 0x23b
+#define EE_AUDIO_LB_B_STS 0x23c
+
+/*
+ * AUDIO LOCKER
+ */
+#define AUD_LOCK_EN 0x000
+#define AUD_LOCK_SW_RESET 0x001
+#define AUD_LOCK_SW_LATCH 0x002
+#define AUD_LOCK_HW_LATCH 0x003
+#define AUD_LOCK_REFCLK_SRC 0x004
+#define AUD_LOCK_REFCLK_LAT_INT 0x005
+#define AUD_LOCK_IMCLK_LAT_INT 0x006
+#define AUD_LOCK_OMCLK_LAT_INT 0x007
+#define AUD_LOCK_REFCLK_DS_INT 0x008
+#define AUD_LOCK_IMCLK_DS_INT 0x009
+#define AUD_LOCK_OMCLK_DS_INT 0x00a
+#define AUD_LOCK_INT_CLR 0x00b
+#define AUD_LOCK_GCLK_CTRL 0x00c
+#define AUD_LOCK_INT_CTRL 0x00d
+#define RO_REF2IMCLK_CNT_L 0x010
+#define RO_REF2IMCLK_CNT_H 0x011
+#define RO_REF2OMCLK_CNT_L 0x012
+#define RO_REF2OMCLK_CNT_H 0x013
+#define RO_IMCLK2REF_CNT_L 0x014
+#define RO_IMCLK2REF_CNT_H 0x015
+#define RO_OMCLK2REF_CNT_L 0x016
+#define RO_OMCLK2REF_CNT_H 0x017
+#define RO_REFCLK_PKG_CNT 0x018
+#define RO_IMCLK_PKG_CNT 0x019
+#define RO_OMCLK_PKG_CNT 0x01a
+#define RO_AUD_LOCK_INT_STATUS 0x01b
+
+/*
+ * EQ DRC, g12a, g12b
+ */
+#define AED_EQ_CH1_COEF00 0x00
+#define AED_EQ_CH1_COEF01 0x01
+#define AED_EQ_CH1_COEF02 0x02
+#define AED_EQ_CH1_COEF03 0x03
+#define AED_EQ_CH1_COEF04 0x04
+#define AED_EQ_CH1_COEF10 0x05
+#define AED_EQ_CH1_COEF11 0x06
+#define AED_EQ_CH1_COEF12 0x07
+#define AED_EQ_CH1_COEF13 0x08
+#define AED_EQ_CH1_COEF14 0x09
+#define AED_EQ_CH1_COEF20 0x0a
+#define AED_EQ_CH1_COEF21 0x0b
+#define AED_EQ_CH1_COEF22 0x0c
+#define AED_EQ_CH1_COEF23 0x0d
+#define AED_EQ_CH1_COEF24 0x0e
+#define AED_EQ_CH1_COEF30 0x0f
+#define AED_EQ_CH1_COEF31 0x10
+#define AED_EQ_CH1_COEF32 0x11
+#define AED_EQ_CH1_COEF33 0x12
+#define AED_EQ_CH1_COEF34 0x13
+#define AED_EQ_CH1_COEF40 0x14
+#define AED_EQ_CH1_COEF41 0x15
+#define AED_EQ_CH1_COEF42 0x16
+#define AED_EQ_CH1_COEF43 0x17
+#define AED_EQ_CH1_COEF44 0x18
+#define AED_EQ_CH1_COEF50 0x19
+#define AED_EQ_CH1_COEF51 0x1a
+#define AED_EQ_CH1_COEF52 0x1b
+#define AED_EQ_CH1_COEF53 0x1c
+#define AED_EQ_CH1_COEF54 0x1d
+#define AED_EQ_CH1_COEF60 0x1e
+#define AED_EQ_CH1_COEF61 0x1f
+#define AED_EQ_CH1_COEF62 0x20
+#define AED_EQ_CH1_COEF63 0x21
+#define AED_EQ_CH1_COEF64 0x22
+#define AED_EQ_CH1_COEF70 0x23
+#define AED_EQ_CH1_COEF71 0x24
+#define AED_EQ_CH1_COEF72 0x25
+#define AED_EQ_CH1_COEF73 0x26
+#define AED_EQ_CH1_COEF74 0x27
+#define AED_EQ_CH1_COEF80 0x28
+#define AED_EQ_CH1_COEF81 0x29
+#define AED_EQ_CH1_COEF82 0x2a
+#define AED_EQ_CH1_COEF83 0x2b
+#define AED_EQ_CH1_COEF84 0x2c
+#define AED_EQ_CH1_COEF90 0x2d
+#define AED_EQ_CH1_COEF91 0x2e
+#define AED_EQ_CH1_COEF92 0x2f
+#define AED_EQ_CH1_COEF93 0x30
+#define AED_EQ_CH1_COEF94 0x31
+#define AED_EQ_CH2_COEF00 0x32
+#define AED_EQ_CH2_COEF01 0x33
+#define AED_EQ_CH2_COEF02 0x34
+#define AED_EQ_CH2_COEF03 0x35
+#define AED_EQ_CH2_COEF04 0x36
+#define AED_EQ_CH2_COEF10 0x37
+#define AED_EQ_CH2_COEF11 0x38
+#define AED_EQ_CH2_COEF12 0x39
+#define AED_EQ_CH2_COEF13 0x3a
+#define AED_EQ_CH2_COEF14 0x3b
+#define AED_EQ_CH2_COEF20 0x3c
+#define AED_EQ_CH2_COEF21 0x3d
+#define AED_EQ_CH2_COEF22 0x3e
+#define AED_EQ_CH2_COEF23 0x3f
+#define AED_EQ_CH2_COEF24 0x40
+#define AED_EQ_CH2_COEF30 0x41
+#define AED_EQ_CH2_COEF31 0x42
+#define AED_EQ_CH2_COEF32 0x43
+#define AED_EQ_CH2_COEF33 0x44
+#define AED_EQ_CH2_COEF34 0x45
+#define AED_EQ_CH2_COEF40 0x46
+#define AED_EQ_CH2_COEF41 0x47
+#define AED_EQ_CH2_COEF42 0x48
+#define AED_EQ_CH2_COEF43 0x49
+#define AED_EQ_CH2_COEF44 0x4a
+#define AED_EQ_CH2_COEF50 0x4b
+#define AED_EQ_CH2_COEF51 0x4c
+#define AED_EQ_CH2_COEF52 0x4d
+#define AED_EQ_CH2_COEF53 0x4e
+#define AED_EQ_CH2_COEF54 0x4f
+#define AED_EQ_CH2_COEF60 0x50
+#define AED_EQ_CH2_COEF61 0x51
+#define AED_EQ_CH2_COEF62 0x52
+#define AED_EQ_CH2_COEF63 0x53
+#define AED_EQ_CH2_COEF64 0x54
+#define AED_EQ_CH2_COEF70 0x55
+#define AED_EQ_CH2_COEF71 0x56
+#define AED_EQ_CH2_COEF72 0x57
+#define AED_EQ_CH2_COEF73 0x58
+#define AED_EQ_CH2_COEF74 0x59
+#define AED_EQ_CH2_COEF80 0x5a
+#define AED_EQ_CH2_COEF81 0x5b
+#define AED_EQ_CH2_COEF82 0x5c
+#define AED_EQ_CH2_COEF83 0x5d
+#define AED_EQ_CH2_COEF84 0x5e
+#define AED_EQ_CH2_COEF90 0x5f
+#define AED_EQ_CH2_COEF91 0x60
+#define AED_EQ_CH2_COEF92 0x61
+#define AED_EQ_CH2_COEF93 0x62
+#define AED_EQ_CH2_COEF94 0x63
+#define AED_EQ_EN_G12X 0x64
+#define AED_EQ_VOLUME_G12X 0x65
+#define AED_EQ_VOLUME_SLEW_CNT_G12X 0x66
+#define AED_MUTE_G12X 0x67
+#define AED_DRC_EN 0x68
+#define AED_DRC_AE 0x69
+#define AED_DRC_AA 0x6a
+#define AED_DRC_AD 0x6b
+#define AED_DRC_AE_1M 0x6c
+#define AED_DRC_AA_1M 0x6d
+#define AED_DRC_AD_1M 0x6e
+#define AED_DRC_OFFSET0 0x6f
+#define AED_DRC_OFFSET1 0x70
+#define AED_DRC_THD0_G12X 0x71
+#define AED_DRC_THD1_G12X 0x72
+#define AED_DRC_K0_G12X 0x73
+#define AED_DRC_K1_G12X 0x74
+#define AED_CLIP_THD_G12X 0x75
+#define AED_NG_THD0 0x76
+#define AED_NG_THD1 0x77
+#define AED_NG_CNT_THD 0x78
+#define AED_NG_CTL 0x79
+#define AED_ED_CTL 0x7a
+#define AED_DEBUG0 0x7b
+#define AED_DEBUG1 0x7c
+#define AED_DEBUG2 0x7d
+#define AED_DEBUG3 0x7e
+#define AED_DEBUG4 0x7f
+#define AED_DEBUG5 0x80
+#define AED_DEBUG6 0x81
+#define AED_DRC_AA_H 0x82
+#define AED_DRC_AD_H 0x83
+#define AED_DRC_AA_1M_H 0x84
+#define AED_DRC_AD_1M_H 0x85
+#define AED_NG_CNT 0x86
+#define AED_NG_STEP 0x87
+/*
+ * EQ DRC, New ARCH, from tl1
+ */
+#define AED_COEF_RAM_CNTL 0x00
+#define AED_COEF_RAM_DATA 0x01
+#define AED_EQ_EN 0x02
+#define AED_EQ_TAP_CNTL 0x03
+#define AED_EQ_VOLUME 0x04
+#define AED_EQ_VOLUME_SLEW_CNT 0x05
+#define AED_MUTE 0x06
+#define AED_DRC_CNTL 0x07
+#define AED_DRC_RMS_COEF0 0x08
+#define AED_DRC_RMS_COEF1 0x09
+#define AED_DRC_THD0 0x0a
+#define AED_DRC_THD1 0x0b
+#define AED_DRC_THD2 0x0c
+#define AED_DRC_THD3 0x0d
+#define AED_DRC_THD4 0x0e
+#define AED_DRC_K0 0x0f
+#define AED_DRC_K1 0x10
+#define AED_DRC_K2 0x11
+#define AED_DRC_K3 0x12
+#define AED_DRC_K4 0x13
+#define AED_DRC_K5 0x14
+#define AED_DRC_THD_OUT0 0x15
+#define AED_DRC_THD_OUT1 0x16
+#define AED_DRC_THD_OUT2 0x17
+#define AED_DRC_THD_OUT3 0x18
+#define AED_DRC_OFFSET 0x19
+#define AED_DRC_RELEASE_COEF00 0x1a
+#define AED_DRC_RELEASE_COEF01 0x1b
+#define AED_DRC_RELEASE_COEF10 0x1c
+#define AED_DRC_RELEASE_COEF11 0x1d
+#define AED_DRC_RELEASE_COEF20 0x1e
+#define AED_DRC_RELEASE_COEF21 0x1f
+#define AED_DRC_RELEASE_COEF30 0x20
+#define AED_DRC_RELEASE_COEF31 0x21
+#define AED_DRC_RELEASE_COEF40 0x22
+#define AED_DRC_RELEASE_COEF41 0x23
+#define AED_DRC_RELEASE_COEF50 0x24
+#define AED_DRC_RELEASE_COEF51 0x25
+#define AED_DRC_ATTACK_COEF00 0x26
+#define AED_DRC_ATTACK_COEF01 0x27
+#define AED_DRC_ATTACK_COEF10 0x28
+#define AED_DRC_ATTACK_COEF11 0x29
+#define AED_DRC_ATTACK_COEF20 0x2a
+#define AED_DRC_ATTACK_COEF21 0x2b
+#define AED_DRC_ATTACK_COEF30 0x2c
+#define AED_DRC_ATTACK_COEF31 0x2d
+#define AED_DRC_ATTACK_COEF40 0x2e
+#define AED_DRC_ATTACK_COEF41 0x2f
+#define AED_DRC_ATTACK_COEF50 0x30
+#define AED_DRC_ATTACK_COEF51 0x31
+#define AED_DRC_LOOPBACK_CNTL 0x32
+#define AED_MDRC_CNTL 0x33
+#define AED_MDRC_RMS_COEF00 0x34
+#define AED_MDRC_RMS_COEF01 0x35
+#define AED_MDRC_RELEASE_COEF00 0x36
+#define AED_MDRC_RELEASE_COEF01 0x37
+#define AED_MDRC_ATTACK_COEF00 0x38
+#define AED_MDRC_ATTACK_COEF01 0x39
+#define AED_MDRC_THD0 0x3a
+#define AED_MDRC_K0 0x3b
+#define AED_MDRC_LOW_GAIN 0x3c
+#define AED_MDRC_OFFSET0 0x3d
+#define AED_MDRC_RMS_COEF10 0x3e
+#define AED_MDRC_RMS_COEF11 0x3f
+#define AED_MDRC_RELEASE_COEF10 0x40
+#define AED_MDRC_RELEASE_COEF11 0x41
+#define AED_MDRC_ATTACK_COEF10 0x42
+#define AED_MDRC_ATTACK_COEF11 0x43
+#define AED_MDRC_THD1 0x44
+#define AED_MDRC_K1 0x45
+#define AED_MDRC_OFFSET1 0x46
+#define AED_MDRC_MID_GAIN 0x47
+#define AED_MDRC_RMS_COEF20 0x48
+#define AED_MDRC_RMS_COEF21 0x49
+#define AED_MDRC_RELEASE_COEF20 0x4a
+#define AED_MDRC_RELEASE_COEF21 0x4b
+#define AED_MDRC_ATTACK_COEF20 0x4c
+#define AED_MDRC_ATTACK_COEF21 0x4d
+#define AED_MDRC_THD2 0x4e
+#define AED_MDRC_K2 0x4f
+#define AED_MDRC_OFFSET2 0x50
+#define AED_MDRC_HIGH_GAIN 0x51
+#define AED_ED_CNTL 0x52
+#define AED_DC_EN 0x53
+#define AED_ND_LOW_THD 0x54
+#define AED_ND_HIGH_THD 0x55
+#define AED_ND_CNT_THD 0x56
+#define AED_ND_SUM_NUM 0x57
+#define AED_ND_CZ_NUM 0x58
+#define AED_ND_SUM_THD0 0x59
+#define AED_ND_SUM_THD1 0x5a
+#define AED_ND_CZ_THD0 0x5b
+#define AED_ND_CZ_THD1 0x5c
+#define AED_ND_COND_CNTL 0x5d
+#define AED_ND_RELEASE_COEF0 0x5e
+#define AED_ND_RELEASE_COEF1 0x5f
+#define AED_ND_ATTACK_COEF0 0x60
+#define AED_ND_ATTACK_COEF1 0x61
+#define AED_ND_CNTL 0x62
+#define AED_MIX0_LL 0x63
+#define AED_MIX0_RL 0x64
+#define AED_MIX0_LR 0x65
+#define AED_MIX0_RR 0x66
+#define AED_CLIP_THD 0x67
+#define AED_CH1_ND_SUM_OUT 0x68
+#define AED_CH2_ND_SUM_OUT 0x69
+#define AED_CH1_ND_CZ_OUT 0x6a
+#define AED_CH2_ND_CZ_OUT 0x6b
+#define AED_NOISE_STATUS 0x6c
+#define AED_POW_CURRENT_S0 0x6d
+#define AED_POW_CURRENT_S1 0x6e
+#define AED_POW_CURRENT_S2 0x6f
+#define AED_POW_OUT0 0x70
+#define AED_POW_OUT1 0x71
+#define AED_POW_OUT2 0x72
+#define AED_POW_ADJ_INDEX0 0x73
+#define AED_POW_ADJ_INDEX1 0x74
+#define AED_POW_ADJ_INDEX2 0x75
+#define AED_DRC_GAIN_INDEX0 0x76
+#define AED_DRC_GAIN_INDEX1 0x77
+#define AED_DRC_GAIN_INDEX2 0x78
+#define AED_CH1_VOLUME_STATE 0x79
+#define AED_CH2_VOLUME_STATE 0x7a
+#define AED_CH1_VOLUME_GAIN 0x7b
+#define AED_CH2_VOLUME_GAIN 0x7c
+#define AED_FULL_POW_CURRENT 0x7d
+#define AED_FULL_POW_OUT 0x7e
+#define AED_FULL_POW_ADJ 0x7f
+#define AED_FULL_DRC_GAIN 0x80
+#define AED_MASTER_VOLUME_STATE 0x81
+#define AED_MASTER_VOLUME_GAIN 0x82
+
+#define AED_TOP_CTL 0x88
+#define AED_TOP_REQ_CTL 0x89
+
+/*
+ * VAD, Voice activity detection
+ */
+#define VAD_TOP_CTRL0 0x000
+#define VAD_TOP_CTRL1 0x001
+#define VAD_TOP_CTRL2 0x002
+#define VAD_FIR_CTRL 0x003
+#define VAD_FIR_EMP 0x004
+#define VAD_FIR_COEF0 0x005
+#define VAD_FIR_COEF1 0x006
+#define VAD_FIR_COEF2 0x007
+#define VAD_FIR_COEF3 0x008
+#define VAD_FIR_COEF4 0x009
+#define VAD_FIR_COEF5 0x00a
+#define VAD_FIR_COEF6 0x00b
+#define VAD_FIR_COEF7 0x00c
+#define VAD_FIR_COEF8 0x00d
+#define VAD_FIR_COEF9 0x00e
+#define VAD_FIR_COEF10 0x00f
+#define VAD_FIR_COEF11 0x010
+#define VAD_FIR_COEF12 0x011
+#define VAD_FRAME_CTRL0 0x012
+#define VAD_FRAME_CTRL1 0x013
+#define VAD_FRAME_CTRL2 0x014
+#define VAD_CEP_CTRL0 0x015
+#define VAD_CEP_CTRL1 0x016
+#define VAD_CEP_CTRL2 0x017
+#define VAD_CEP_CTRL3 0x018
+#define VAD_CEP_CTRL4 0x019
+#define VAD_CEP_CTRL5 0x01a
+#define VAD_DEC_CTRL 0x01b
+#define VAD_TOP_STS0 0x01c
+#define VAD_TOP_STS1 0x01d
+#define VAD_TOP_STS2 0x01e
+#define VAD_FIR_STS0 0x01f
+#define VAD_FIR_STS1 0x020
+#define VAD_POW_STS0 0x021
+#define VAD_POW_STS1 0x022
+#define VAD_POW_STS2 0x023
+#define VAD_FFT_STS0 0x024
+#define VAD_FFT_STS1 0x025
+#define VAD_SPE_STS0 0x026
+#define VAD_SPE_STS1 0x027
+#define VAD_SPE_STS2 0x028
+#define VAD_SPE_STS3 0x029
+#define VAD_DEC_STS0 0x02a
+#define VAD_DEC_STS1 0x02b
+#define VAD_LUT_CTRL 0x02c
+#define VAD_LUT_WR 0x02d
+#define VAD_LUT_RD 0x02e
+#define VAD_IN_SEL0 0x02f
+#define VAD_IN_SEL1 0x030
+#define VAD_TO_DDR 0x031
+
#endif
#define SPDIF_B 1
/* Debug by PTM when bringup */
-/* #define G12A_PTM */
+/*#define __PTM_SPDIF_CLK__*/
/* for debug */
/*#define __SPDIFIN_INSERT_CHNUM__*/
}
mpll_freq = p_spdif->sysclk_freq * mul;
-#ifdef G12A_PTM
- mpll_freq = p_spdif->sysclk_freq * 57;
+#ifdef __PTM_SPDIF_CLK__
+ mpll_freq = p_spdif->sysclk_freq * 58;
#endif
pr_info("\t finally sys freq:%d, mpll freq:%d\n",
p_spdif->sysclk_freq,
freq,
dir);
- if (dir == SND_SOC_CLOCK_OUT) {
+ if (clk_id == 0) {
struct aml_spdif *p_spdif = snd_soc_dai_get_drvdata(cpu_dai);
p_spdif->sysclk_freq = freq;
.eq_drc_en = true,
};
+struct spdif_chipinfo tl1_spdif_a_chipinfo = {
+ .id = SPDIF_A,
+ .chnum_en = true,
+ .hold_start = true,
+ .eq_drc_en = true,
+};
+
+struct spdif_chipinfo tl1_spdif_b_chipinfo = {
+ .id = SPDIF_B,
+ .chnum_en = true,
+ .hold_start = true,
+ .eq_drc_en = true,
+};
+
static const struct of_device_id aml_spdif_device_id[] = {
{
.compatible = "amlogic, axg-snd-spdif",
- .data = &axg_spdif_chipinfo,
+ .data = &axg_spdif_chipinfo,
},
{
.compatible = "amlogic, g12a-snd-spdif-a",
- .data = &g12a_spdif_a_chipinfo,
+ .data = &g12a_spdif_a_chipinfo,
},
{
.compatible = "amlogic, g12a-snd-spdif-b",
- .data = &g12a_spdif_b_chipinfo,
+ .data = &g12a_spdif_b_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-spdif-a",
+ .data = &tl1_spdif_a_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-spdif-b",
+ .data = &tl1_spdif_b_chipinfo,
},
{},
};
#include <linux/amlogic/media/sound/aout_notify.h>
/*#define G12A_PTM*/
-/*#define G12A_PTM_LB_INTERNAL*/
+/*#define __PTM_SPDIF_INTERNAL_LB__*/
unsigned int aml_spdif_ctrl_read(struct aml_audio_controller *actrl,
int stream, int index)
} else {
aml_audiobus_update_bits(actrl,
EE_AUDIO_SPDIFIN_CTRL0, 1<<31, is_enable<<31);
-#ifdef G12A_PTM_LB_INTERNAL
+#ifdef __PTM_SPDIF_INTERNAL_LB__
if (index == 0)
aml_audiobus_update_bits(actrl,
EE_AUDIO_SPDIFIN_CTRL0, 0x3<<4, 0x1<<4);
#include "ddr_mngr.h"
#include "tdm_hw.h"
-/*#define G12A_PTM*/
+/*#define __PTM_TDM_CLK__*/
#include "sharebuffer.h"
return -EINVAL;
}
+ if (toddr_src_get() == FRHDMIRX) {
+ src = FRHDMIRX;
+
+ tdm_update_slot_in(p_tdm->actrl, p_tdm->id, HDMIRX_I2S);
+ }
+
+ pr_info("%s Expected toddr src:%s\n",
+ __func__,
+ toddr_src_get_str(src));
+
fmt.type = toddr_type;
fmt.msb = 31;
fmt.lsb = lsb;
p_tdm->setting.sysclk = freq;
-#ifdef G12A_PTM
+#ifdef __PTM_TDM_CLK__
if (p_tdm->id == 0)
ratio = 14;
else if (p_tdm->id == 1)
- ratio = 18;
+ ratio = 18 * 2;
else if (p_tdm->id == 2)
ratio = 20;
#endif
};
static const struct snd_soc_component_driver aml_tdm_component = {
- .name = DRV_NAME,
+ .name = DRV_NAME,
};
struct tdm_chipinfo axg_tdma_chipinfo = {
- .id = TDM_A,
+ .id = TDM_A,
};
struct tdm_chipinfo axg_tdmb_chipinfo = {
- .id = TDM_B,
+ .id = TDM_B,
};
struct tdm_chipinfo axg_tdmc_chipinfo = {
- .id = TDM_C,
+ .id = TDM_C,
};
struct tdm_chipinfo g12a_tdma_chipinfo = {
- .id = TDM_A,
+ .id = TDM_A,
.sclk_ws_inv = true,
.oe_fn = true,
.clk_pad_ctl = true,
};
struct tdm_chipinfo g12a_tdmb_chipinfo = {
- .id = TDM_B,
+ .id = TDM_B,
.sclk_ws_inv = true,
.oe_fn = true,
.clk_pad_ctl = true,
};
struct tdm_chipinfo g12a_tdmc_chipinfo = {
- .id = TDM_C,
+ .id = TDM_C,
+ .sclk_ws_inv = true,
+ .oe_fn = true,
+ .clk_pad_ctl = true,
+ .same_src_fn = true,
+};
+
+struct tdm_chipinfo tl1_tdma_chipinfo = {
+ .id = TDM_A,
+ .sclk_ws_inv = true,
+ .oe_fn = true,
+ .clk_pad_ctl = true,
+ .same_src_fn = true,
+};
+
+struct tdm_chipinfo tl1_tdmb_chipinfo = {
+ .id = TDM_B,
+ .sclk_ws_inv = true,
+ .oe_fn = true,
+ .clk_pad_ctl = true,
+ .same_src_fn = true,
+};
+
+struct tdm_chipinfo tl1_tdmc_chipinfo = {
+ .id = TDM_C,
.sclk_ws_inv = true,
.oe_fn = true,
.clk_pad_ctl = true,
static const struct of_device_id aml_tdm_device_id[] = {
{
.compatible = "amlogic, axg-snd-tdma",
- .data = &axg_tdma_chipinfo,
+ .data = &axg_tdma_chipinfo,
},
{
.compatible = "amlogic, axg-snd-tdmb",
- .data = &axg_tdmb_chipinfo,
+ .data = &axg_tdmb_chipinfo,
},
{
.compatible = "amlogic, axg-snd-tdmc",
- .data = &axg_tdmc_chipinfo,
+ .data = &axg_tdmc_chipinfo,
},
{
.compatible = "amlogic, g12a-snd-tdma",
- .data = &g12a_tdma_chipinfo,
+ .data = &g12a_tdma_chipinfo,
},
{
.compatible = "amlogic, g12a-snd-tdmb",
- .data = &g12a_tdmb_chipinfo,
+ .data = &g12a_tdmb_chipinfo,
},
{
.compatible = "amlogic, g12a-snd-tdmc",
- .data = &g12a_tdmc_chipinfo,
+ .data = &g12a_tdmc_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-tdma",
+ .data = &tl1_tdma_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-tdmb",
+ .data = &tl1_tdmb_chipinfo,
+ },
+ {
+ .compatible = "amlogic, tl1-snd-tdmc",
+ .data = &tl1_tdmc_chipinfo,
},
{},
};
#define MST_CLK_INVERT_PH2_TDMOUT_BCLK (1 << 4)
#define MST_CLK_INVERT_PH2_TDMOUT_FCLK (1 << 5)
-/*#define G12A_PTM*/
/*#define G12A_PTM_LB_INTERNAL*/
+/*#define TL1_PTM_LB_INTERNAL*/
/* without audio handler, it should be improved */
void aml_tdm_enable(
pr_debug("sclk_ph0 (pad) clk ctl set:%x\n", clkctl);
/* clk ctrl: delay line and invert clk */
/*clkctl |= 0x88880000;*/
-#ifdef G12A_PTM
- clkctl |= 0x77777700;
-#endif
+
if (master_mode) {
off_set = EE_AUDIO_MST_B_SCLK_CTRL1 - EE_AUDIO_MST_A_SCLK_CTRL1;
reg_out = EE_AUDIO_MST_A_SCLK_CTRL1 + off_set * id;
offset = EE_AUDIO_TDMIN_B_CTRL - EE_AUDIO_TDMIN_A_CTRL;
reg = EE_AUDIO_TDMIN_A_CTRL + offset * index;
-#ifdef G12A_PTM_LB_INTERNAL
+#if defined(G12A_PTM_LB_INTERNAL)
if (index == 0) /*TODO: ptm, tdma dsp_a lb*/
aml_audiobus_update_bits(actrl, reg,
0xf<<20|0x1f, 6<<20|(slot_width-1));
aml_audiobus_update_bits(actrl, reg,
0xf<<20|0x1f, 7<<20|(slot_width-1));
else
+#elif defined(TL1_PTM_LB_INTERNAL)
+if (index == 0) /*TODO: ptm, tdma dsp_a lb*/
+ aml_audiobus_update_bits(actrl, reg,
+ 0xf<<20|0x1f, 13<<20|(slot_width-1));
+else if (index == 1) /*TODO: ptm, tdmb i2s lb*/
+ aml_audiobus_update_bits(actrl, reg,
+ 0xf<<20|0x1f, 14<<20|(slot_width-1));
+else
#endif
aml_audiobus_update_bits(actrl, reg,
0xf << 20 | 0x1f, in_src << 20 | (slot_width-1));
}
+void tdm_update_slot_in(
+ struct aml_audio_controller *actrl,
+ int index, int in_src)
+{
+ unsigned int reg, offset;
+
+ offset = EE_AUDIO_TDMIN_B_CTRL - EE_AUDIO_TDMIN_A_CTRL;
+ reg = EE_AUDIO_TDMIN_A_CTRL + offset * index;
+
+ aml_audiobus_update_bits(actrl, reg,
+ 0xf << 20, in_src << 20);
+}
+
void aml_tdm_set_channel_mask(
struct aml_audio_controller *actrl,
int stream, int index, int lane, int mask)
pr_err("unknown tdm mpad:%d\n", mpad);
return;
}
- reg = EE_AUDIO_MST_PAD_CTRL0;
+ reg = EE_AUDIO_MST_PAD_CTRL0(0);
aml_audiobus_update_bits(actrl, reg,
mask_offset, val_offset);
- reg = EE_AUDIO_MST_PAD_CTRL1;
+ reg = EE_AUDIO_MST_PAD_CTRL1(0);
switch (tdm_index) {
case 0:
mask_offset = 0x7 << 16 | 0x7 << 0;
#include "audio_io.h"
#include "regs.h"
+// TODO: fix me, now based by tl1
+enum tdmin_src {
+ PAD_TDMINA_DIN = 0,
+ PAD_TDMINB_DIN = 1,
+ PAD_TDMINC_DIN = 2,
+ PAD_TDMINA_D = 4,
+ PAD_TDMINB_D = 5,
+ PAD_TDMINC_D = 6,
+ HDMIRX_I2S = 7,
+ ACODEC_ADC = 8,
+ TDMOUTA = 13,
+ TDMOUTB = 14,
+ TDMOUTC = 15,
+};
+
struct pcm_setting {
unsigned int pcm_mode;
unsigned int sysclk;
struct aml_audio_controller *actrl,
int index, int in_src, int slot_width);
+extern void tdm_update_slot_in(
+ struct aml_audio_controller *actrl,
+ int index, int in_src);
+
extern void aml_tdm_set_channel_mask(
struct aml_audio_controller *actrl,
int stream, int index, int lanes, int mask);
--- /dev/null
+/*
+ * sound/soc/amlogic/auge/tl1,clocks.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#undef pr_fmt
+#define pr_fmt(fmt) "tl1_clocks: " fmt
+
+#include <dt-bindings/clock/amlogic,tl1-audio-clk.h>
+
+#include "audio_clks.h"
+#include "regs.h"
+
+static spinlock_t aclk_lock;
+
+static const char *const mclk_parent_names[] = {"mpll0", "mpll1",
+ "mpll2", "mpll3", "hifi_pll", "fclk_div3", "fclk_div4", "gp0_pll"};
+
+static const char *const audioclk_parent_names[] = {
+ "mclk_a", "mclk_b", "mclk_c", "mclk_d", "mclk_e",
+ "mclk_f", "i_slv_sclk_a", "i_slv_sclk_b", "i_slv_sclk_c",
+ "i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g",
+ "i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"};
+
+CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0);
+CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1);
+CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2);
+CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3);
+CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4);
+CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5);
+CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6);
+CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7);
+CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8);
+CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9);
+CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10);
+CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11);
+CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12);
+CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13);
+CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14);
+CLOCK_GATE(audio_loopbacka, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15);
+CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16);
+CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17);
+CLOCK_GATE(audio_resamplea, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18);
+CLOCK_GATE(audio_reserved0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19);
+CLOCK_GATE(audio_reserved1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 20);
+CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 21);
+CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 22);
+CLOCK_GATE(audio_resampleb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 26);
+CLOCK_GATE(audio_tovad, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 27);
+CLOCK_GATE(audio_audiolocker, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 28);
+CLOCK_GATE(audio_spdifin_lb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 29);
+CLOCK_GATE(audio_fratv, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 30);
+CLOCK_GATE(audio_frhdmirx, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 31);
+
+CLOCK_GATE(audio_frddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 0);
+CLOCK_GATE(audio_toddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 1);
+CLOCK_GATE(audio_loopbackb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 2);
+
+static struct clk_gate *tl1_audio_clk_gates[] = {
+ &audio_ddr_arb,
+ &audio_pdm,
+ &audio_tdmina,
+ &audio_tdminb,
+ &audio_tdminc,
+ &audio_tdminlb,
+ &audio_tdmouta,
+ &audio_tdmoutb,
+ &audio_tdmoutc,
+ &audio_frddra,
+ &audio_frddrb,
+ &audio_frddrc,
+ &audio_toddra,
+ &audio_toddrb,
+ &audio_toddrc,
+ &audio_loopbacka,
+ &audio_spdifin,
+ &audio_spdifout,
+ &audio_resamplea,
+ &audio_reserved0,
+ &audio_reserved1,
+ &audio_spdifoutb,
+ &audio_eqdrc,
+ &audio_resampleb,
+ &audio_tovad,
+ &audio_audiolocker,
+ &audio_spdifin_lb,
+ &audio_fratv,
+ &audio_frhdmirx,
+
+ &audio_frddrd,
+ &audio_toddrd,
+ &audio_loopbackb,
+};
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw *tl1_audio_clk_hws[] = {
+ [CLKID_AUDIO_DDR_ARB] = &audio_ddr_arb.hw,
+ [CLKID_AUDIO_PDM] = &audio_pdm.hw,
+ [CLKID_AUDIO_TDMINA] = &audio_tdmina.hw,
+ [CLKID_AUDIO_TDMINB] = &audio_tdminb.hw,
+ [CLKID_AUDIO_TDMINC] = &audio_tdminc.hw,
+ [CLKID_AUDIO_TDMINLB] = &audio_tdminlb.hw,
+ [CLKID_AUDIO_TDMOUTA] = &audio_tdmouta.hw,
+ [CLKID_AUDIO_TDMOUTB] = &audio_tdmoutb.hw,
+ [CLKID_AUDIO_TDMOUTC] = &audio_tdmoutc.hw,
+ [CLKID_AUDIO_FRDDRA] = &audio_frddra.hw,
+ [CLKID_AUDIO_FRDDRB] = &audio_frddrb.hw,
+ [CLKID_AUDIO_FRDDRC] = &audio_frddrc.hw,
+ [CLKID_AUDIO_TODDRA] = &audio_toddra.hw,
+ [CLKID_AUDIO_TODDRB] = &audio_toddrb.hw,
+ [CLKID_AUDIO_TODDRC] = &audio_toddrc.hw,
+ [CLKID_AUDIO_LOOPBACKA] = &audio_loopbacka.hw,
+ [CLKID_AUDIO_SPDIFIN] = &audio_spdifin.hw,
+ [CLKID_AUDIO_SPDIFOUT] = &audio_spdifout.hw,
+ [CLKID_AUDIO_RESAMPLEA] = &audio_resamplea.hw,
+ [CLKID_AUDIO_RESERVED0] = &audio_reserved0.hw,
+ [CLKID_AUDIO_RESERVED1] = &audio_reserved1.hw,
+ [CLKID_AUDIO_SPDIFOUTB] = &audio_spdifoutb.hw,
+ [CLKID_AUDIO_EQDRC] = &audio_eqdrc.hw,
+ [CLKID_AUDIO_RESAMPLEB] = &audio_resampleb.hw,
+ [CLKID_AUDIO_TOVAD] = &audio_tovad.hw,
+ [CLKID_AUDIO_AUDIOLOCKER] = &audio_audiolocker.hw,
+ [CLKID_AUDIO_SPDIFIN_LB] = &audio_spdifin_lb.hw,
+ [CLKID_AUDIO_FRATV] = &audio_fratv.hw,
+ [CLKID_AUDIO_FRHDMIRX] = &audio_frhdmirx.hw,
+ [CLKID_AUDIO_FRDDRD] = &audio_frddrd.hw,
+ [CLKID_AUDIO_TODDRD] = &audio_toddrd.hw,
+ [CLKID_AUDIO_LOOPBACKB] = &audio_loopbackb.hw,
+};
+
+static int tl1_clk_gates_init(struct clk **clks, void __iomem *iobase)
+{
+ int clkid;
+
+ if (ARRAY_SIZE(tl1_audio_clk_gates) != MCLK_BASE) {
+ pr_err("check clk gates number\n");
+ return -EINVAL;
+ }
+
+ for (clkid = 0; clkid < MCLK_BASE; clkid++) {
+ tl1_audio_clk_gates[clkid]->reg = iobase;
+ clks[clkid] = clk_register(NULL, tl1_audio_clk_hws[clkid]);
+ WARN_ON(IS_ERR_OR_NULL(clks[clkid]));
+ }
+
+ return 0;
+}
+
+/* mclk_a */
+CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 31);
+/* mclk_b */
+CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 31);
+/* mclk_c */
+CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 31);
+/* mclk_d */
+CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 31);
+/* mclk_e */
+CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 31);
+/* mclk_f */
+CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0x7, 24);
+CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0, 16);
+CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 31);
+/* spdifin */
+CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24);
+CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8);
+CLOCK_COM_GATE(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 31);
+/* spdifout */
+CLOCK_COM_MUX(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0x7, 24);
+CLOCK_COM_DIV(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0, 10);
+CLOCK_COM_GATE(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 31);
+/* pdmin0 */
+CLOCK_COM_MUX(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0x7, 24);
+CLOCK_COM_DIV(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0, 16);
+CLOCK_COM_GATE(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 31);
+/* pdmin1 */
+CLOCK_COM_MUX(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0x7, 24);
+CLOCK_COM_DIV(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0, 16);
+CLOCK_COM_GATE(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 31);
+/* spdifout b*/
+CLOCK_COM_MUX(spdifout_b,
+ AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0x7, 24);
+CLOCK_COM_DIV(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0, 10);
+CLOCK_COM_GATE(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 31);
+/* audio locker_out */
+CLOCK_COM_MUX(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 24);
+CLOCK_COM_DIV(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 16, 8);
+CLOCK_COM_GATE(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 31);
+/* audio locker_in */
+CLOCK_COM_MUX(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 8);
+CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8);
+CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15);
+/* audio resample */
+CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24);
+CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 8);
+CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31);
+
+static int tl1_clks_init(struct clk **clks, void __iomem *iobase)
+{
+ IOMAP_COM_CLK(mclk_a, iobase);
+ clks[CLKID_AUDIO_MCLK_A] = REGISTER_CLK_COM(mclk_a);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_A]));
+
+ IOMAP_COM_CLK(mclk_b, iobase);
+ clks[CLKID_AUDIO_MCLK_B] = REGISTER_CLK_COM(mclk_b);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_B]));
+
+ IOMAP_COM_CLK(mclk_c, iobase);
+ clks[CLKID_AUDIO_MCLK_C] = REGISTER_CLK_COM(mclk_c);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_C]));
+
+ IOMAP_COM_CLK(mclk_d, iobase);
+ clks[CLKID_AUDIO_MCLK_D] = REGISTER_CLK_COM(mclk_d);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_D]));
+
+ IOMAP_COM_CLK(mclk_e, iobase);
+ clks[CLKID_AUDIO_MCLK_E] = REGISTER_CLK_COM(mclk_e);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_E]));
+
+ IOMAP_COM_CLK(mclk_f, iobase);
+ clks[CLKID_AUDIO_MCLK_F] = REGISTER_CLK_COM(mclk_f);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_F]));
+
+ IOMAP_COM_CLK(spdifin, iobase);
+ clks[CLKID_AUDIO_SPDIFIN_CTRL] = REGISTER_CLK_COM(spdifin);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFIN_CTRL]));
+
+ IOMAP_COM_CLK(spdifout, iobase);
+ clks[CLKID_AUDIO_SPDIFOUT_CTRL] = REGISTER_CLK_COM(spdifout);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUT_CTRL]));
+
+ IOMAP_COM_CLK(pdmin0, iobase);
+ clks[CLKID_AUDIO_PDMIN0] = REGISTER_CLK_COM(pdmin0);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN0]));
+
+ IOMAP_COM_CLK(pdmin1, iobase);
+ clks[CLKID_AUDIO_PDMIN1] = REGISTER_CLK_COM(pdmin1);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN1]));
+
+ IOMAP_COM_CLK(spdifout_b, iobase);
+ clks[CLKID_AUDIO_SPDIFOUTB_CTRL] = REGISTER_CLK_COM(spdifout_b);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUTB_CTRL]));
+
+ IOMAP_COM_CLK(locker_out, iobase);
+ clks[CLKID_AUDIO_LOCKER_OUT] = REGISTER_AUDIOCLK_COM(locker_out);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_OUT]));
+
+ IOMAP_COM_CLK(locker_in, iobase);
+ clks[CLKID_AUDIO_LOCKER_IN] = REGISTER_AUDIOCLK_COM(locker_in);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_IN]));
+
+ IOMAP_COM_CLK(resample, iobase);
+ clks[CLKID_AUDIO_RESAMPLE_CTRL] = REGISTER_AUDIOCLK_COM(resample);
+ WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_RESAMPLE_CTRL]));
+
+ return 0;
+}
+
+struct audio_clk_init tl1_audio_clks_init = {
+ .clk_num = NUM_AUDIO_CLKS,
+ .clk_gates = tl1_clk_gates_init,
+ .clks = tl1_clks_init,
+};
projects / platform / kernel / linux-amlogic.git / commitdiff