arm64: zynqmp: Update device tree for pinmux

Added pin control support in device tree for zynqmp.

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 66dc110a964cab8032ae1a7ce8127f8e429b81ca..eb361b00362ae8863b00c7598c9aa4253935d161 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
 / {
        model = "ZynqMP ZCU102 RevA";
@@ -68,6 +69,8 @@
 
 &can1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1_default>;
 };
 
 &dcc {
@@ -120,6 +123,8 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem3_default>;
        phy0: phy@21 {
                reg = <21>;
                ti,rx-internal-delay = <0x8>;
@@ -130,6 +135,8 @@
 
 &gpio {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
 &gpu {
@@ -139,6 +146,11 @@
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 
        tca6416_u97: gpio@20 {
                /*
@@ -400,6 +412,12 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1_default>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
        /* FIXME PL i2c via PCA9306 - u45 */
        /* FIXME MSP430 - u41 - not detected */
        i2cswitch@74 { /* u34 */
@@ -549,6 +567,269 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
        };
 };
 
+&pinctrl0 {
+       status = "okay";
+       pinctrl_i2c0_default: i2c0-default {
+               mux {
+                       groups = "i2c0_3_grp";
+                       function = "i2c0";
+               };
+
+               conf {
+                       groups = "i2c0_3_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_14_grp", "gpio0_15_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_14_grp", "gpio0_15_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_default: i2c1-default {
+               mux {
+                       groups = "i2c1_4_grp";
+                       function = "i2c1";
+               };
+
+               conf {
+                       groups = "i2c1_4_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio {
+               mux {
+                       groups = "gpio0_16_grp", "gpio0_17_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_16_grp", "gpio0_17_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               mux {
+                       groups = "uart0_4_grp";
+                       function = "uart0";
+               };
+
+               conf {
+                       groups = "uart0_4_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO18";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO19";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_uart1_default: uart1-default {
+               mux {
+                       groups = "uart1_5_grp";
+                       function = "uart1";
+               };
+
+               conf {
+                       groups = "uart1_5_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO21";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO20";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_usb0_default: usb0-default {
+               mux {
+                       groups = "usb0_0_grp";
+                       function = "usb0";
+               };
+
+               conf {
+                       groups = "usb0_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO52", "MIO53", "MIO55";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+                              "MIO60", "MIO61", "MIO62", "MIO63";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_gem3_default: gem3-default {
+               mux {
+                       function = "ethernet3";
+                       groups = "ethernet3_0_grp";
+               };
+
+               conf {
+                       groups = "ethernet3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+                                                                       "MIO75";
+                       bias-high-impedance;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+                                                                       "MIO69";
+                       bias-disable;
+                       low-power-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio3";
+                       groups = "mdio3_0_grp";
+               };
+
+               conf-mdio {
+                       groups = "mdio3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+       };
+
+       pinctrl_can1_default: can1-default {
+               mux {
+                       function = "can1";
+                       groups = "can1_6_grp";
+               };
+
+               conf {
+                       groups = "can1_6_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO25";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO24";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_sdhci1_default: sdhci1-default {
+               mux {
+                       groups = "sdio1_0_grp";
+                       function = "sdio1";
+               };
+
+               conf {
+                       groups = "sdio1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+
+               mux-cd {
+                       groups = "sdio1_0_cd_grp";
+                       function = "sdio1_cd";
+               };
+
+               conf-cd {
+                       groups = "sdio1_0_cd_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-wp {
+                       groups = "sdio1_0_wp_grp";
+                       function = "sdio1_wp";
+               };
+
+               conf-wp {
+                       groups = "sdio1_0_wp_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_gpio_default: gpio-default {
+               mux-sw {
+                       function = "gpio0";
+                       groups = "gpio0_22_grp", "gpio0_23_grp";
+               };
+
+               conf-sw {
+                       groups = "gpio0_22_grp", "gpio0_23_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-msp {
+                       function = "gpio0";
+                       groups = "gpio0_13_grp", "gpio0_38_grp";
+               };
+
+               conf-msp {
+                       groups = "gpio0_13_grp", "gpio0_38_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-pull-up {
+                       pins = "MIO22", "MIO23";
+                       bias-pull-up;
+               };
+
+               conf-pull-none {
+                       pins = "MIO13", "MIO38";
+                       bias-disable;
+               };
+       };
+};
+
 &pcie {
        status = "okay";
 };
@@ -603,21 +884,29 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhci1_default>;
        no-1-8-v;       /* for 1.0 silicon */
        xlnx,mio_bank = <1>;
 };
 
 &uart0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 /* ULPI SMSC USB3320 */
 &usb0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb0_default>;
 };
 
 &dwc3_0 {

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 07b99233b3d291e10a9c1e1d9d0e61dc726848f8..54e0edbbb9a3ae2c41685117d4fdbc00bd5a36cb 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -830,6 +830,12 @@
                        power-domains = <&pd_sd1>;
                };
 
+               pinctrl0: pinctrl@ff180000 {
+                       compatible = "xlnx,pinctrl-zynqmp";
+                       status = "disabled";
+                       reg = <0x0 0xff180000 0x0 0x1000>;
+               };
+
                smmu: smmu@fd800000 {
                        compatible = "arm,mmu-500";
                        reg = <0x0 0xfd800000 0x0 0x20000>;

diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644 (file)
index 0000000..e1b81fe
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,30 @@
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2017 Xilinx, Inc.
+ * Author: Chirag Parekh <chirag.parekh@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for IO standards */
+#define IO_STANDARD_LVCMOS33      0
+#define IO_STANDARD_LVCMOS18      1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST            0
+#define SLEW_RATE_SLOW            1
+
+/* Bit values for Pin inputs */
+#define PIN_INPUT_TYPE_CMOS       0
+#define PIN_INPUT_TYPE_SCHMITT    1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */