#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA 0x40
/*
* Micron MT41J128M16HA-15E
* */
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
int i;
+
popts->clk_adjust = 4;
popts->cpo_override = 0x1f;
popts->write_data_delay = 4;
popts->trwt_override = 1;
popts->trwt = 0;
+ if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+ popts->ecc_mode = 0;
+
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
#define CONFIG_BAUDRATE 115200
+#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \