pinctrl: renesas: r8a779g0: Add missing SCIF1_X

This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 4e6e295..609fa44 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -301,13 +301,13 @@
 #define IP0SR1_15_12   FM(MSIOF1_SCK)          FM(HSCK3_A)             FM(CTS3_N)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR1_19_16   FM(MSIOF1_TXD)          FM(HRX3_A)              FM(SCK3)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR1_23_20   FM(MSIOF1_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              FM(TX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              FM(RX1_X)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP1SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           FM(CTS1_N_X)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           FM(RTS1_N_X)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             FM(SCK1_X)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -817,19 +817,24 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP0SR1_27_24,  MSIOF0_SS2),
        PINMUX_IPSR_GPSR(IP0SR1_27_24,  HTX1_X),
+       PINMUX_IPSR_GPSR(IP0SR1_27_24,  TX1_X),
 
        PINMUX_IPSR_GPSR(IP0SR1_31_28,  MSIOF0_SS1),
        PINMUX_IPSR_GPSR(IP0SR1_31_28,  HRX1_X),
+       PINMUX_IPSR_GPSR(IP0SR1_31_28,  RX1_X),
 
        /* IP1SR1 */
        PINMUX_IPSR_GPSR(IP1SR1_3_0,    MSIOF0_SYNC),
        PINMUX_IPSR_GPSR(IP1SR1_3_0,    HCTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    CTS1_N_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_7_4,    MSIOF0_TXD),
        PINMUX_IPSR_GPSR(IP1SR1_7_4,    HRTS1_N_X),
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    RTS1_N_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_11_8,   MSIOF0_SCK),
        PINMUX_IPSR_GPSR(IP1SR1_11_8,   HSCK1_X),
+       PINMUX_IPSR_GPSR(IP1SR1_11_8,   SCK1_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_15_12,  MSIOF0_RXD),
 
@@ -2180,6 +2185,29 @@ static const unsigned int scif1_ctrl_mux[] = {
        RTS1_N_MARK, CTS1_N_MARK,
 };
 
+/* - SCIF1_X ------------------------------------------------------------------ */
+static const unsigned int scif1_data_x_pins[] = {
+       /* RX1_X, TX1_X */
+       RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scif1_data_x_mux[] = {
+       RX1_X_MARK, TX1_X_MARK,
+};
+static const unsigned int scif1_clk_x_pins[] = {
+       /* SCK1_X */
+       RCAR_GP_PIN(1, 10),
+};
+static const unsigned int scif1_clk_x_mux[] = {
+       SCK1_X_MARK,
+};
+static const unsigned int scif1_ctrl_x_pins[] = {
+       /* RTS1_N_X, CTS1_N_X */
+       RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scif1_ctrl_x_mux[] = {
+       RTS1_N_X_MARK, CTS1_N_X_MARK,
+};
+
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
        /* RX3, TX3 */
@@ -2500,9 +2528,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(scif0_data),
        SH_PFC_PIN_GROUP(scif0_clk),
        SH_PFC_PIN_GROUP(scif0_ctrl),
-       SH_PFC_PIN_GROUP(scif1_data),
-       SH_PFC_PIN_GROUP(scif1_clk),
-       SH_PFC_PIN_GROUP(scif1_ctrl),
+       SH_PFC_PIN_GROUP(scif1_data),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_clk),            /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_ctrl),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_data_x),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_clk_x),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(scif1_ctrl_x),         /* suffix might be updated */
        SH_PFC_PIN_GROUP(scif3_data),           /* suffix might be updated */
        SH_PFC_PIN_GROUP(scif3_clk),            /* suffix might be updated */
        SH_PFC_PIN_GROUP(scif3_ctrl),           /* suffix might be updated */
@@ -2785,9 +2816,13 @@ static const char * const scif0_groups[] = {
 };
 
 static const char * const scif1_groups[] = {
+       /* suffix might be updated */
        "scif1_data",
        "scif1_clk",
        "scif1_ctrl",
+       "scif1_data_x",
+       "scif1_clk_x",
+       "scif1_ctrl_x",
 };
 
 static const char * const scif3_groups[] = {