--- /dev/null
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+This file is used to generate m32r-asm.c.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include <ctype.h>
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "m32r-opc.h"
+
+/* ??? The layout of this stuff is still work in progress.
+ For speed in assembly/disassembly, we use inline functions. That of course
+ will only work for GCC. When this stuff is finished, we can decide whether
+ to keep the inline functions (and only get the performance increase when
+ compiled with GCC), or switch to macros, or use something else.
+*/
+
+static const char *parse_insn_normal
+ PARAMS ((const struct cgen_insn *, const char **, struct cgen_fields *));
+static void insert_insn_normal
+ PARAMS ((const struct cgen_insn *, struct cgen_fields *, cgen_insn_t *));
+\f
+/* Default insertion routine.
+
+ SHIFT is negative for left shifts, positive for right shifts.
+ All bits of VALUE to be inserted must be valid as we don't handle
+ signed vs unsigned shifts.
+
+ ATTRS is a mask of the boolean attributes. We don't need any at the
+ moment, but for consistency with extract_normal we have them. */
+
+/* FIXME: This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* FIXME: For architectures where insns can be representable as ints,
+ store insn in `field' struct and add registers, etc. while parsing. */
+
+static CGEN_INLINE void
+insert_normal (value, attrs, start, length, shift, total_length, buffer)
+ long value;
+ unsigned int attrs;
+ int start, length, shift, total_length;
+ char *buffer;
+{
+ bfd_vma x;
+
+#if 0 /*def CGEN_INT_INSN*/
+ *buffer |= ((value & ((1 << length) - 1))
+ << (total_length - (start + length)));
+#else
+ switch (total_length)
+ {
+ case 8:
+ x = *(unsigned char *) buffer;
+ break;
+ case 16:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ x = bfd_getb16 (buffer);
+ else
+ x = bfd_getl16 (buffer);
+ break;
+ case 32:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ x = bfd_getb32 (buffer);
+ else
+ x = bfd_getl32 (buffer);
+ break;
+ default :
+ abort ();
+ }
+
+ if (shift < 0)
+ value <<= -shift;
+ else
+ value >>= shift;
+
+ x |= ((value & ((1 << length) - 1))
+ << (total_length - (start + length)));
+
+ switch (total_length)
+ {
+ case 8:
+ *buffer = value;
+ break;
+ case 16:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ bfd_putb16 (x, buffer);
+ else
+ bfd_putl16 (x, buffer);
+ break;
+ case 32:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ bfd_putb32 (x, buffer);
+ else
+ bfd_putl32 (x, buffer);
+ break;
+ default :
+ abort ();
+ }
+#endif
+}
+\f
+/* -- assembler routines inserted here */
+/* -- asm.c */
+
+/* Handle shigh(), high(). */
+
+static const char *
+parse_h_hi16 (strp, opindex, min, max, valuep)
+ const char **strp;
+ int opindex;
+ unsigned long min, max;
+ unsigned long *valuep;
+{
+ const char *errmsg;
+
+ /* FIXME: Need # in assembler syntax (means '#' is optional). */
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncmp (*strp, "high(", 5) == 0)
+ {
+ *strp += 5;
+ /* FIXME: If value was a number, right shift by 16. */
+ errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO, valuep);
+ if (**strp != ')')
+ return "missing `)'";
+ ++*strp;
+ return errmsg;
+ }
+ else if (strncmp (*strp, "shigh(", 6) == 0)
+ {
+ *strp += 6;
+ /* FIXME: If value was a number, right shift by 16 (+ sign test). */
+ errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO, valuep);
+ if (**strp != ')')
+ return "missing `)'";
+ ++*strp;
+ return errmsg;
+ }
+
+ return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+}
+
+/* Handle low() in a signed context. Also handle sda().
+ The signedness of the value doesn't matter to low(), but this also
+ handles the case where low() isn't present. */
+
+static const char *
+parse_h_slo16 (strp, opindex, min, max, valuep)
+ const char **strp;
+ int opindex;
+ long min, max;
+ long *valuep;
+{
+ const char *errmsg;
+
+ /* FIXME: Need # in assembler syntax (means '#' is optional). */
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncmp (*strp, "low(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep);
+ if (**strp != ')')
+ return "missing `)'";
+ ++*strp;
+ return errmsg;
+ }
+
+ if (strncmp (*strp, "sda(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, valuep);
+ if (**strp != ')')
+ return "missing `)'";
+ ++*strp;
+ return errmsg;
+ }
+
+ return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
+}
+
+/* Handle low() in an unsigned context.
+ The signedness of the value doesn't matter to low(), but this also
+ handles the case where low() isn't present. */
+
+static const char *
+parse_h_ulo16 (strp, opindex, min, max, valuep)
+ const char **strp;
+ int opindex;
+ unsigned long min, max;
+ unsigned long *valuep;
+{
+ const char *errmsg;
+
+ /* FIXME: Need # in assembler syntax (means '#' is optional). */
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncmp (*strp, "low(", 4) == 0)
+ {
+ *strp += 4;
+ errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep);
+ if (**strp != ')')
+ return "missing `)'";
+ ++*strp;
+ return errmsg;
+ }
+
+ return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+}
+
+/* -- */
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers.
+*/
+
+CGEN_INLINE const char *
+m32r_cgen_parse_operand (opindex, strp, fields)
+ int opindex;
+ const char **strp;
+ struct cgen_fields *fields;
+{
+ const char *errmsg;
+
+ switch (opindex)
+ {
+ case 0 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
+ break;
+ case 1 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
+ break;
+ case 2 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
+ break;
+ case 3 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
+ break;
+ case 4 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2);
+ break;
+ case 5 :
+ errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1);
+ break;
+ case 6 :
+ errmsg = cgen_parse_signed_integer (strp, 6, -128, 127, &fields->f_simm8);
+ break;
+ case 7 :
+ errmsg = cgen_parse_signed_integer (strp, 7, -32768, 32767, &fields->f_simm16);
+ break;
+ case 8 :
+ errmsg = cgen_parse_unsigned_integer (strp, 8, 0, 15, &fields->f_uimm4);
+ break;
+ case 9 :
+ errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 31, &fields->f_uimm5);
+ break;
+ case 10 :
+ errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 65535, &fields->f_uimm16);
+ break;
+ case 11 :
+ errmsg = parse_h_hi16 (strp, 11, 0, 65535, &fields->f_hi16);
+ break;
+ case 12 :
+ errmsg = parse_h_slo16 (strp, 12, -32768, 32767, &fields->f_simm16);
+ break;
+ case 13 :
+ errmsg = parse_h_ulo16 (strp, 13, 0, 65535, &fields->f_uimm16);
+ break;
+ case 14 :
+ errmsg = cgen_parse_address (strp, 14, 0, &fields->f_uimm24);
+ break;
+ case 15 :
+ errmsg = cgen_parse_address (strp, 15, 0, &fields->f_disp8);
+ break;
+ case 16 :
+ errmsg = cgen_parse_address (strp, 16, 0, &fields->f_disp16);
+ break;
+ case 17 :
+ errmsg = cgen_parse_address (strp, 17, 0, &fields->f_disp24);
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+/* Main entry point for operand insertion.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. It's also needed by GAS to insert operands that couldn't be
+ resolved during parsing.
+*/
+
+CGEN_INLINE void
+m32r_cgen_insert_operand (opindex, fields, buffer)
+ int opindex;
+ struct cgen_fields *fields;
+ cgen_insn_t *buffer;
+{
+ switch (opindex)
+ {
+ case 0 :
+ insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 1 :
+ insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 2 :
+ insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 3 :
+ insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 4 :
+ insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 5 :
+ insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 6 :
+ insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 7 :
+ insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 8 :
+ insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 9 :
+ insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 10 :
+ insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 11 :
+ insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 12 :
+ insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 13 :
+ insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 14 :
+ insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 15 :
+ insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 16 :
+ insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case 17 :
+ insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while building insn.\n",
+ opindex);
+ abort ();
+ }
+}
+
+/* Main entry point for operand validation.
+
+ This function is called from GAS when it has fully resolved an operand
+ that couldn't be resolved during parsing.
+
+ The result is NULL for success or an error message (which may be
+ computed into a static buffer).
+*/
+
+CGEN_INLINE const char *
+m32r_cgen_validate_operand (opindex, fields)
+ int opindex;
+ const struct cgen_fields *fields;
+{
+ const char *errmsg = NULL;
+
+ switch (opindex)
+ {
+ case 0 :
+ /* nothing to do */
+ break;
+ case 1 :
+ /* nothing to do */
+ break;
+ case 2 :
+ /* nothing to do */
+ break;
+ case 3 :
+ /* nothing to do */
+ break;
+ case 4 :
+ /* nothing to do */
+ break;
+ case 5 :
+ /* nothing to do */
+ break;
+ case 6 :
+ errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
+ break;
+ case 7 :
+ errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+ break;
+ case 8 :
+ errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
+ break;
+ case 9 :
+ errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
+ break;
+ case 10 :
+ errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+ break;
+ case 11 :
+ errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
+ break;
+ case 12 :
+ errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+ break;
+ case 13 :
+ errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+ break;
+ case 14 :
+ /* nothing to do */
+ break;
+ case 15 :
+ /* nothing to do */
+ break;
+ case 16 :
+ /* nothing to do */
+ break;
+ case 17 :
+ /* nothing to do */
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while validating operand.\n",
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn *m32r_cgen_parse_handlers[] = {
+ 0, /* default */
+ parse_insn_normal,
+};
+
+cgen_insert_fn *m32r_cgen_insert_handlers[] = {
+ 0, /* default */
+ insert_insn_normal,
+};
+
+void
+m32r_cgen_init_asm (mach, endian)
+ int mach;
+ enum cgen_endian endian;
+{
+ m32r_cgen_init_tables (mach);
+ cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
+ cgen_asm_init ();
+}
+
+\f
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure.
+*/
+
+static const char *
+parse_insn_normal (insn, strp, fields)
+ const struct cgen_insn *insn;
+ const char **strp;
+ struct cgen_fields *fields;
+{
+ const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const unsigned char *syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ int past_opcode_p;
+#endif
+
+ /* If mnemonics are constant, they're not stored with the syntax string. */
+#ifndef CGEN_MNEMONIC_OPERANDS
+ {
+ const char *p = syntax->mnemonic;
+
+ while (*p && *p == *str)
+ ++p, ++str;
+ if (*p || (*str && !isspace (*str)))
+ return "unrecognized instruction";
+
+ while (isspace (*str))
+ ++str;
+ }
+#endif
+
+ CGEN_INIT_PARSE ();
+ cgen_asm_init_parse ();
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ for (syn = syntax->syntax; *syn != '\0'; )
+ {
+ /* Non operand chars must match exactly. */
+ /* FIXME: Need to better handle whitespace. */
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ if (*str == CGEN_SYNTAX_CHAR (*syn))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (*syn == ' ')
+ past_opcode_p = 1;
+#endif
+ ++syn;
+ ++str;
+ }
+ else
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ /* FIXME: would like to return "expected char `c'" */
+ return "syntax error";
+ }
+ continue;
+ }
+
+ /* We have an operand of some sort. */
+ errmsg = m32r_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn),
+ &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (*syn == '\0')
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (isspace (*str))
+ ++str;
+
+ if (*str != '\0')
+ return "junk at end of line"; /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return "unrecognized instruction";
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in target byte order. */
+
+static void
+insert_insn_normal (insn, fields, buffer)
+ const struct cgen_insn *insn;
+ struct cgen_fields *fields;
+ cgen_insn_t *buffer;
+{
+ const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ bfd_vma value;
+ const unsigned char *syn;
+
+ CGEN_INIT_INSERT ();
+ value = syntax->value;
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#if 0 /*def CGEN_INT_INSN*/
+ *buffer = value;
+#else
+ switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields)))
+ {
+ case 8:
+ *buffer = value;
+ break;
+ case 16:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ bfd_putb16 (value, (char *) buffer);
+ else
+ bfd_putl16 (value, (char *) buffer);
+ break;
+ case 32:
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ bfd_putb32 (value, (char *) buffer);
+ else
+ bfd_putl32 (value, (char *) buffer);
+ break;
+ default:
+ abort ();
+ }
+#endif
+
+ /* ??? Rather than scanning the syntax string again, we could store
+ in `fields' a null terminated list of the fields that are present. */
+
+ for (syn = syntax->syntax; *syn != '\0'; ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer);
+ }
+}
+\f
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed). */
+
+const struct cgen_insn *
+m32r_cgen_assemble_insn (str, fields, buf)
+ const char *str;
+ struct cgen_fields *fields;
+ cgen_insn_t *buf;
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+
+ /* Skip leading white space. */
+ while (isspace (*str))
+ ++str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (str);
+
+ /* Keep looking until we find a match. */
+
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const struct cgen_insn *insn = ilist->insn;
+
+#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
+ /* Is this insn supported by the selected cpu? */
+ if (! m32r_cgen_insn_supported (insn))
+ continue;
+#endif
+
+#if 1 /* FIXME: wip */
+ /* If the RELAX attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0)
+ continue;
+#endif
+
+ str = start;
+
+ /* Record a default length for the insn. This will get set to the
+ correct value while parsing. */
+ /* FIXME: wip */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ /* ??? The extent to which moving the parse and insert handlers into
+ this function (thus removing the function call) will speed things up
+ is unclear. The simplicity and flexibility of the current scheme is
+ appropriate for now. One could have the best of both worlds with
+ inline functions but of course that would only work for gcc. Since
+ we're machine generating some code we could do that here too. Maybe
+ later. */
+ if (! (*CGEN_PARSE_FN (insn)) (insn, &str, fields))
+ {
+ (*CGEN_INSERT_FN (insn)) (insn, fields, buf);
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ /* Try the next entry. */
+ }
+
+ /* FIXME: Define this as a callback, or pass back string? */
+ as_bad ("bad instruction `%s'", start);
+ return NULL;
+}
+\f
+/* Record each member of OPVALS in the assembler's symbol table.
+ FIXME: Not currently used. */
+
+void
+m32r_cgen_asm_hash_keywords (opvals)
+ struct cgen_keyword *opvals;
+{
+ struct cgen_keyword_search search = cgen_keyword_search_init (opvals, NULL);
+ const struct cgen_keyword_entry *ke;
+
+ while ((ke = cgen_keyword_search_next (&search)) != NULL)
+ {
+#if 0 /* Unnecessary, should be done in the search routine. */
+ if (! m32r_cgen_opval_supported (ke))
+ continue;
+#endif
+ cgen_asm_record_register (ke->name, ke->value);
+ }
+}
--- /dev/null
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+This file is used to generate m32r-dis.c.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "m32r-opc.h"
+#include "bfd.h"
+
+/* ??? The layout of this stuff is still work in progress.
+ For speed in assembly/disassembly, we use inline functions. That of course
+ will only work for GCC. When this stuff is finished, we can decide whether
+ to keep the inline functions (and only get the performance increase when
+ compiled with GCC), or switch to macros, or use something else.
+*/
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG "*unknown*"
+
+/* FIXME: Machine generate. */
+#ifndef CGEN_PCREL_OFFSET
+#define CGEN_PCREL_OFFSET 0
+#endif
+
+static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int));
+
+static int extract_insn_normal
+ PARAMS ((const struct cgen_insn *, void *, cgen_insn_t, struct cgen_fields *));
+static void print_insn_normal
+ PARAMS ((void *, const struct cgen_insn *, struct cgen_fields *, bfd_vma, int));
+\f
+/* Default extraction routine.
+
+ ATTRS is a mask of the boolean attributes. We only need `unsigned',
+ but for generality we take a bitmask of all of them. */
+
+static int
+extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
+ void *buf_ctrl;
+ cgen_insn_t insn_value;
+ unsigned int attrs;
+ int start, length, shift, total_length;
+ long *valuep;
+{
+ long value;
+
+#ifdef CGEN_INT_INSN
+#if 0
+ value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
+ & ((1 << length) - 1));
+#else
+ value = ((insn_value >> (total_length - (start + length)))
+ & ((1 << length) - 1));
+#endif
+ if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ && (value & (1 << (length - 1))))
+ value -= 1 << length;
+#else
+ /* FIXME: unfinished */
+#endif
+
+ /* This is backwards as we undo the effects of insert_normal. */
+ if (shift < 0)
+ value >>= -shift;
+ else
+ value <<= shift;
+
+ *valuep = value;
+ return 1;
+}
+
+/* Default print handler. */
+
+static void
+print_normal (dis_info, value, attrs, pc, length)
+ void *dis_info;
+ long value;
+ unsigned int attrs;
+ unsigned long pc; /* FIXME: should be bfd_vma */
+ int length;
+{
+ disassemble_info *info = dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE))
+ ; /* nothing to do (??? at least not yet) */
+ else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
+ /* ??? Not all cases of this are currently caught. */
+ else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR))
+ /* FIXME: Why & 0xffffffff? */
+ (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
+ else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+ else
+ (*info->fprintf_func) (info->stream, "%ld", value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (dis_info, keyword_table, value, attrs)
+ void *dis_info;
+ struct cgen_keyword *keyword_table;
+ long value;
+ CGEN_ATTR *attrs;
+{
+ disassemble_info *info = dis_info;
+ const struct cgen_keyword_entry *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+\f
+/* -- disassembler routines inserted here */
+/* -- dis.c */
+
+#undef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN my_print_insn
+
+static int
+my_print_insn (pc, info, buf, buflen)
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+{
+ unsigned long insn_value;
+
+ /* 32 bit insn? */
+ if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+ return print_insn (pc, info, buf, buflen);
+
+ /* Print the first insn. */
+ if ((pc & 3) == 0)
+ {
+ if (print_insn (pc, info, buf, 16) == 0)
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ buf += 2;
+ }
+
+ if (buf[0] & 0x80)
+ {
+ /* Parallel. */
+ (*info->fprintf_func) (info->stream, " || ");
+ buf[0] &= 0x7f;
+ }
+ else
+ (*info->fprintf_func) (info->stream, " -> ");
+
+ /* The "& 3" is to ensure the branch address is computed correctly
+ [if it is a branch]. */
+ if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+
+ return (pc & 3) ? 2 : 4;
+}
+
+/* -- */
+
+/* Main entry point for operand extraction.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers.
+*/
+
+CGEN_INLINE int
+m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
+ int opindex;
+ void *buf_ctrl;
+ cgen_insn_t insn_value;
+ struct cgen_fields *fields;
+{
+ int length;
+
+ switch (opindex)
+ {
+ case 0 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ break;
+ case 1 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ break;
+ case 2 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ break;
+ case 3 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ break;
+ case 4 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ break;
+ case 5 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ break;
+ case 6 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8);
+ break;
+ case 7 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
+ break;
+ case 8 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm4);
+ break;
+ case 9 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm5);
+ break;
+ case 10 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
+ break;
+ case 11 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_hi16);
+ break;
+ case 12 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
+ break;
+ case 13 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
+ break;
+ case 14 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm24);
+ break;
+ case 15 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp8);
+ break;
+ case 16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp16);
+ break;
+ case 17 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp24);
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
+ opindex);
+ abort ();
+ }
+
+ return length;
+}
+
+/* Main entry point for printing operands.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers.
+*/
+
+CGEN_INLINE void
+m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
+ int opindex;
+ disassemble_info *info;
+ struct cgen_fields *fields;
+ int attrs;
+ bfd_vma pc;
+ int length;
+{
+ switch (opindex)
+ {
+ case 0 :
+ print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 1 :
+ print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 2 :
+ print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 3 :
+ print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 4 :
+ print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 5 :
+ print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case 6 :
+ print_normal (info, fields->f_simm8, 0, pc, length);
+ break;
+ case 7 :
+ print_normal (info, fields->f_simm16, 0, pc, length);
+ break;
+ case 8 :
+ print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 9 :
+ print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 10 :
+ print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 11 :
+ print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 12 :
+ print_normal (info, fields->f_simm16, 0, pc, length);
+ break;
+ case 13 :
+ print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 14 :
+ print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case 15 :
+ print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case 16 :
+ print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case 17 :
+ print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while printing insn.\n",
+ opindex);
+ abort ();
+ }
+}
+
+cgen_extract_fn *m32r_cgen_extract_handlers[] = {
+ 0, /* default */
+ extract_insn_normal,
+};
+
+cgen_print_fn *m32r_cgen_print_handlers[] = {
+ 0, /* default */
+ print_insn_normal,
+};
+
+
+void
+m32r_cgen_init_dis (mach, endian)
+ int mach;
+ enum cgen_endian endian;
+{
+ m32r_cgen_init_tables (mach);
+ cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
+ cgen_dis_init ();
+}
+
+\f
+/* Default insn extractor.
+
+ The extracted fields are stored in DIS_FLDS.
+ BUF_CTRL is used to handle reading variable length insns (FIXME: not done).
+ Return the length of the insn in bits, or 0 if no match. */
+
+static int
+extract_insn_normal (insn, buf_ctrl, insn_value, fields)
+ const struct cgen_insn *insn;
+ void *buf_ctrl;
+ cgen_insn_t insn_value;
+ struct cgen_fields *fields;
+{
+ const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ const unsigned char *syn;
+
+ /* ??? Some of the operand extract routines need to know the insn length,
+ which might be computed as we go. Set a default value and it'll be
+ modified as necessary. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT ();
+
+ for (syn = syntax->syntax; *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn),
+ buf_ctrl, insn_value, fields);
+ if (length == 0)
+ return 0;
+ }
+
+ /* We recognized and successfully extracted this insn.
+ If a length is recorded with this insn, it has a fixed length.
+ Otherwise we require the syntax string to have a fake operand which
+ sets the `length' field in `flds'. */
+ /* FIXME: wip */
+ if (syntax->length > 0)
+ return syntax->length;
+ return fields->length;
+}
+
+/* Default insn printer.
+
+ DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ about disassemble_info.
+*/
+
+static void
+print_insn_normal (dis_info, insn, fields, pc, length)
+ void *dis_info;
+ const struct cgen_insn *insn;
+ struct cgen_fields *fields;
+ bfd_vma pc;
+ int length;
+{
+ const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = dis_info;
+ const unsigned char *syn;
+
+ CGEN_INIT_PRINT ();
+
+ for (syn = syntax->syntax; *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+\f
+/* Default value for CGEN_PRINT_INSN.
+ Given BUFLEN bytes (target byte order) read into BUF, look up the
+ insn in the instruction table and disassemble it.
+
+ The result is the size of the insn in bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN print_insn
+#endif
+
+static int
+print_insn (pc, info, buf, buflen)
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+{
+ int i;
+ unsigned long insn_value;
+ const CGEN_INSN_LIST *insn_list;
+
+ switch (buflen)
+ {
+ case 8:
+ insn_value = buf[0];
+ break;
+ case 16:
+ insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
+ break;
+ case 32:
+ insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
+ break;
+ default:
+ abort ();
+ }
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ struct cgen_fields fields;
+ int length;
+
+#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Supported by this cpu? */
+ if (! m32r_cgen_insn_supported (insn))
+ continue;
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+ if ((insn_value & syntax->mask) == syntax->value)
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields);
+ if (length > 0)
+ {
+ (*CGEN_PRINT_FN (insn)) (info, insn, &fields, pc, length);
+ /* length is in bits, result is in bytes */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+int
+print_insn_m32r (pc, info)
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ char buffer[CGEN_MAX_INSN_SIZE];
+ int status, length;
+ static int initialized = 0;
+ static int current_mach = 0;
+ static int current_big_p = 0;
+ int mach = info->mach;
+ int big_p = info->endian == BFD_ENDIAN_BIG;
+
+ /* If we haven't initialized yet, or if we've switched cpu's, initialize. */
+ if (!initialized || mach != current_mach || big_p != current_big_p)
+ {
+ initialized = 1;
+ current_mach = mach;
+ current_big_p = big_p;
+ m32r_cgen_init_dis (mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
+ }
+
+ /* Read enough of the insn so we can look it up in the hash lists. */
+
+ status = (*info->read_memory_func) (pc, buffer, CGEN_BASE_INSN_SIZE, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible, try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE);
+ if (length)
+ return length;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return CGEN_DEFAULT_INSN_SIZE;
+}
--- /dev/null
+/* CGEN support code for m32r.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+
+#include "config.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "bfd.h"
+#include "m32r-opc.h"
+
+struct cgen_keyword_entry m32r_cgen_opval_mach_entries[] = {
+ { "m32r", 0 },
+ { "test", 1 }
+};
+
+struct cgen_keyword m32r_cgen_opval_mach = {
+ & m32r_cgen_opval_mach_entries[0],
+ 2
+};
+
+struct cgen_keyword_entry m32r_cgen_opval_h_gr_entries[] = {
+ { "fp", 13 },
+ { "lr", 14 },
+ { "sp", 15 },
+ { "r0", 0 },
+ { "r1", 1 },
+ { "r2", 2 },
+ { "r3", 3 },
+ { "r4", 4 },
+ { "r5", 5 },
+ { "r6", 6 },
+ { "r7", 7 },
+ { "r8", 8 },
+ { "r9", 9 },
+ { "r10", 10 },
+ { "r11", 11 },
+ { "r12", 12 },
+ { "r13", 13 },
+ { "r14", 14 },
+ { "r15", 15 }
+};
+
+struct cgen_keyword m32r_cgen_opval_h_gr = {
+ & m32r_cgen_opval_h_gr_entries[0],
+ 19
+};
+
+struct cgen_keyword_entry m32r_cgen_opval_h_cr_entries[] = {
+ { "psw", 0 },
+ { "cbr", 1 },
+ { "spi", 2 },
+ { "spu", 3 },
+ { "bpc", 6 },
+ { "cr0", 0 },
+ { "cr1", 1 },
+ { "cr2", 2 },
+ { "cr3", 3 },
+ { "cr4", 4 },
+ { "cr5", 5 },
+ { "cr6", 6 }
+};
+
+struct cgen_keyword m32r_cgen_opval_h_cr = {
+ & m32r_cgen_opval_h_cr_entries[0],
+ 12
+};
+
+
+static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = {
+ { & m32r_cgen_hw_entries[1], "pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
+ { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
+ { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+ { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
+};
+
+
+const struct cgen_operand m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
+{
+/* sr: source register */
+ { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* dr: destination register */
+ { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* src1: source register 1 */
+ { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* src2: source register 2 */
+ { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* scr: source control register */
+ { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* dcr: destination control register */
+ { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* simm8: 8 bit signed immediate */
+ { "simm8", 8, 8, { 0, 0, { 0 } } },
+/* simm16: 16 bit signed immediate */
+ { "simm16", 16, 16, { 0, 0, { 0 } } },
+/* uimm4: 4 bit trap number */
+ { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* uimm5: 5 bit shift count */
+ { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* uimm16: 16 bit unsigned immediate */
+ { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* hi16: high 16 bit immediate, sign optional */
+ { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* slo16: 16 bit signed immediate, for low() */
+ { "slo16", 16, 16, { 0, 0, { 0 } } },
+/* ulo16: 16 bit unsigned immediate, for low() */
+ { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* uimm24: 24 bit address */
+ { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* disp8: 8 bit displacement */
+ { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+/* disp16: 16 bit displacement */
+ { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+/* disp24: 24 bit displacement */
+ { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+};
+
+const struct cgen_insn m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = {
+/* null first entry, end of all hash chains */
+ { { 0 }, { 0 } },
+/* add $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "add $dr,$sr", "add", "add", {'a', 'd', 'd', ' ', 129, ',', 128, }, 0xf0f0, 0xa0, 16 }
+ },
+/* add3 $dr,$sr,$slo16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "add3 $dr,$sr,$slo16", "add3", "add3", {'a', 'd', 'd', '3', ' ', 129, ',', 128, ',', 140, }, 0xf0f00000, 0x80a00000, 32 }
+ },
+/* and $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "and $dr,$sr", "and", "and", {'a', 'n', 'd', ' ', 129, ',', 128, }, 0xf0f0, 0xc0, 16 }
+ },
+/* and3 $dr,$sr,$uimm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "and3 $dr,$sr,$uimm16", "and3", "and3", {'a', 'n', 'd', '3', ' ', 129, ',', 128, ',', 138, }, 0xf0f00000, 0x80c00000, 32 }
+ },
+/* or $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "or $dr,$sr", "or", "or", {'o', 'r', ' ', 129, ',', 128, }, 0xf0f0, 0xe0, 16 }
+ },
+/* or3 $dr,$sr,$ulo16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "or3 $dr,$sr,$ulo16", "or3", "or3", {'o', 'r', '3', ' ', 129, ',', 128, ',', 141, }, 0xf0f00000, 0x80e00000, 32 }
+ },
+/* xor $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "xor $dr,$sr", "xor", "xor", {'x', 'o', 'r', ' ', 129, ',', 128, }, 0xf0f0, 0xd0, 16 }
+ },
+/* xor3 $dr,$sr,$uimm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "xor3 $dr,$sr,$uimm16", "xor3", "xor3", {'x', 'o', 'r', '3', ' ', 129, ',', 128, ',', 138, }, 0xf0f00000, 0x80d00000, 32 }
+ },
+/* addi $dr,$simm8 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "addi $dr,$simm8", "addi", "addi", {'a', 'd', 'd', 'i', ' ', 129, ',', 134, }, 0xf000, 0x4000, 16 }
+ },
+/* addv $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "addv $dr,$sr", "addv", "addv", {'a', 'd', 'd', 'v', ' ', 129, ',', 128, }, 0xf0f0, 0x80, 16 }
+ },
+/* addv3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "addv3 $dr,$sr,$simm16", "addv3", "addv3", {'a', 'd', 'd', 'v', '3', ' ', 129, ',', 128, ',', 135, }, 0xf0f00000, 0x80800000, 32 }
+ },
+/* addx $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "addx $dr,$sr", "addx", "addx", {'a', 'd', 'd', 'x', ' ', 129, ',', 128, }, 0xf0f0, 0x90, 16 }
+ },
+/* bc $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BC)|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bc $disp8", "bc8", "bc", {'b', 'c', ' ', 143, }, 0xff00, 0x7c00, 16 }
+ },
+/* bc.s $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bc.s $disp8", "bc8.s", "bc", {'b', 'c', '.', 's', ' ', 143, }, 0xff00, 0x7c00, 16 }
+ },
+/* bc $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BC)|(1<<CGEN_INSN_RELAX)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bc $disp24", "bc24", "bc", {'b', 'c', ' ', 145, }, 0xff000000, 0xfc000000, 32 }
+ },
+/* bc.l $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bc.l $disp24", "bc24.l", "bc", {'b', 'c', '.', 'l', ' ', 145, }, 0xff000000, 0xfc000000, 32 }
+ },
+/* beq $src1,$src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "beq $src1,$src2,$disp16", "beq", "beq", {'b', 'e', 'q', ' ', 130, ',', 131, ',', 144, }, 0xf0f00000, 0xb0000000, 32 }
+ },
+/* beqz $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "beqz $src2,$disp16", "beqz", "beqz", {'b', 'e', 'q', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0800000, 32 }
+ },
+/* bgez $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bgez $src2,$disp16", "bgez", "bgez", {'b', 'g', 'e', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0b00000, 32 }
+ },
+/* bgtz $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bgtz $src2,$disp16", "bgtz", "bgtz", {'b', 'g', 't', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0d00000, 32 }
+ },
+/* blez $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "blez $src2,$disp16", "blez", "blez", {'b', 'l', 'e', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0c00000, 32 }
+ },
+/* bltz $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bltz $src2,$disp16", "bltz", "bltz", {'b', 'l', 't', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0a00000, 32 }
+ },
+/* bnez $src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bnez $src2,$disp16", "bnez", "bnez", {'b', 'n', 'e', 'z', ' ', 131, ',', 144, }, 0xfff00000, 0xb0900000, 32 }
+ },
+/* bl $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_FILL_SLOT)|(1<<CGEN_INSN_RELAX_BL)|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bl $disp8", "bl8", "bl", {'b', 'l', ' ', 143, }, 0xff00, 0x7e00, 16 }
+ },
+/* bl.s $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_FILL_SLOT)|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bl.s $disp8", "bl8.s", "bl", {'b', 'l', '.', 's', ' ', 143, }, 0xff00, 0x7e00, 16 }
+ },
+/* bl $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BL)|(1<<CGEN_INSN_RELAX)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bl $disp24", "bl24", "bl", {'b', 'l', ' ', 145, }, 0xff000000, 0xfe000000, 32 }
+ },
+/* bl.l $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bl.l $disp24", "bl24.l", "bl", {'b', 'l', '.', 'l', ' ', 145, }, 0xff000000, 0xfe000000, 32 }
+ },
+/* bnc $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BNC)|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bnc $disp8", "bnc8", "bnc", {'b', 'n', 'c', ' ', 143, }, 0xff00, 0x7d00, 16 }
+ },
+/* bnc.s $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bnc.s $disp8", "bnc8.s", "bnc", {'b', 'n', 'c', '.', 's', ' ', 143, }, 0xff00, 0x7d00, 16 }
+ },
+/* bnc $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BNC)|(1<<CGEN_INSN_RELAX)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bnc $disp24", "bnc24", "bnc", {'b', 'n', 'c', ' ', 145, }, 0xff000000, 0xfd000000, 32 }
+ },
+/* bnc.l $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bnc.l $disp24", "bnc24.l", "bnc", {'b', 'n', 'c', '.', 'l', ' ', 145, }, 0xff000000, 0xfd000000, 32 }
+ },
+/* bne $src1,$src2,$disp16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_COND_CTI), { 0 } } },
+ { "bne $src1,$src2,$disp16", "bne", "bne", {'b', 'n', 'e', ' ', 130, ',', 131, ',', 144, }, 0xf0f00000, 0xb0100000, 32 }
+ },
+/* bra $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BRA)|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bra $disp8", "bra8", "bra", {'b', 'r', 'a', ' ', 143, }, 0xff00, 0x7f00, 16 }
+ },
+/* bra.s $disp8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bra.s $disp8", "bra8.s", "bra", {'b', 'r', 'a', '.', 's', ' ', 143, }, 0xff00, 0x7f00, 16 }
+ },
+/* bra $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_RELAX_BRA)|(1<<CGEN_INSN_RELAX)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bra $disp24", "bra24", "bra", {'b', 'r', 'a', ' ', 145, }, 0xff000000, 0xff000000, 32 }
+ },
+/* bra.l $disp24 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "bra.l $disp24", "bra24.l", "bra", {'b', 'r', 'a', '.', 'l', ' ', 145, }, 0xff000000, 0xff000000, 32 }
+ },
+/* cmp $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "cmp $src1,$src2", "cmp", "cmp", {'c', 'm', 'p', ' ', 130, ',', 131, }, 0xf0f0, 0x40, 16 }
+ },
+/* cmpi $src2,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "cmpi $src2,$simm16", "cmpi", "cmpi", {'c', 'm', 'p', 'i', ' ', 131, ',', 135, }, 0xfff00000, 0x80400000, 32 }
+ },
+/* cmpu $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "cmpu $src1,$src2", "cmpu", "cmpu", {'c', 'm', 'p', 'u', ' ', 130, ',', 131, }, 0xf0f0, 0x50, 16 }
+ },
+/* cmpui $src2,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "cmpui $src2,$simm16", "cmpui", "cmpui", {'c', 'm', 'p', 'u', 'i', ' ', 131, ',', 135, }, 0xfff00000, 0x80500000, 32 }
+ },
+/* div $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "div $dr,$sr", "div", "div", {'d', 'i', 'v', ' ', 129, ',', 128, }, 0xf0f0ffff, 0x90000000, 32 }
+ },
+/* divu $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "divu $dr,$sr", "divu", "divu", {'d', 'i', 'v', 'u', ' ', 129, ',', 128, }, 0xf0f0ffff, 0x90100000, 32 }
+ },
+/* rem $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "rem $dr,$sr", "rem", "rem", {'r', 'e', 'm', ' ', 129, ',', 128, }, 0xf0f0ffff, 0x90200000, 32 }
+ },
+/* remu $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "remu $dr,$sr", "remu", "remu", {'r', 'e', 'm', 'u', ' ', 129, ',', 128, }, 0xf0f0ffff, 0x90300000, 32 }
+ },
+/* jl $sr */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_FILL_SLOT)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "jl $sr", "jl", "jl", {'j', 'l', ' ', 128, }, 0xfff0, 0x1ec0, 16 }
+ },
+/* jmp $sr */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "jmp $sr", "jmp", "jmp", {'j', 'm', 'p', ' ', 128, }, 0xfff0, 0x1fc0, 16 }
+ },
+/* ld $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ld $dr,@$sr", "ld", "ld", {'l', 'd', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x20c0, 16 }
+ },
+/* ld $dr,@($sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ld $dr,@($sr)", "ld-2", "ld", {'l', 'd', ' ', 129, ',', '@', '(', 128, ')', }, 0xf0f0, 0x20c0, 16 }
+ },
+/* ld $dr,@($slo16,$sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ld $dr,@($slo16,$sr)", "ld-d", "ld", {'l', 'd', ' ', 129, ',', '@', '(', 140, ',', 128, ')', }, 0xf0f00000, 0xa0c00000, 32 }
+ },
+/* ld $dr,@($sr,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ld $dr,@($sr,$slo16)", "ld-d2", "ld", {'l', 'd', ' ', 129, ',', '@', '(', 128, ',', 140, ')', }, 0xf0f00000, 0xa0c00000, 32 }
+ },
+/* ldb $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldb $dr,@$sr", "ldb", "ldb", {'l', 'd', 'b', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x2080, 16 }
+ },
+/* ldb $dr,@($sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldb $dr,@($sr)", "ldb-2", "ldb", {'l', 'd', 'b', ' ', 129, ',', '@', '(', 128, ')', }, 0xf0f0, 0x2080, 16 }
+ },
+/* ldb $dr,@($slo16,$sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldb $dr,@($slo16,$sr)", "ldb-d", "ldb", {'l', 'd', 'b', ' ', 129, ',', '@', '(', 140, ',', 128, ')', }, 0xf0f00000, 0xa0800000, 32 }
+ },
+/* ldb $dr,@($sr,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldb $dr,@($sr,$slo16)", "ldb-d2", "ldb", {'l', 'd', 'b', ' ', 129, ',', '@', '(', 128, ',', 140, ')', }, 0xf0f00000, 0xa0800000, 32 }
+ },
+/* ldh $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldh $dr,@$sr", "ldh", "ldh", {'l', 'd', 'h', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x20a0, 16 }
+ },
+/* ldh $dr,@($sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldh $dr,@($sr)", "ldh-2", "ldh", {'l', 'd', 'h', ' ', 129, ',', '@', '(', 128, ')', }, 0xf0f0, 0x20a0, 16 }
+ },
+/* ldh $dr,@($slo16,$sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldh $dr,@($slo16,$sr)", "ldh-d", "ldh", {'l', 'd', 'h', ' ', 129, ',', '@', '(', 140, ',', 128, ')', }, 0xf0f00000, 0xa0a00000, 32 }
+ },
+/* ldh $dr,@($sr,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldh $dr,@($sr,$slo16)", "ldh-d2", "ldh", {'l', 'd', 'h', ' ', 129, ',', '@', '(', 128, ',', 140, ')', }, 0xf0f00000, 0xa0a00000, 32 }
+ },
+/* ldub $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldub $dr,@$sr", "ldub", "ldub", {'l', 'd', 'u', 'b', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x2090, 16 }
+ },
+/* ldub $dr,@($sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldub $dr,@($sr)", "ldub-2", "ldub", {'l', 'd', 'u', 'b', ' ', 129, ',', '@', '(', 128, ')', }, 0xf0f0, 0x2090, 16 }
+ },
+/* ldub $dr,@($slo16,$sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldub $dr,@($slo16,$sr)", "ldub-d", "ldub", {'l', 'd', 'u', 'b', ' ', 129, ',', '@', '(', 140, ',', 128, ')', }, 0xf0f00000, 0xa0900000, 32 }
+ },
+/* ldub $dr,@($sr,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldub $dr,@($sr,$slo16)", "ldub-d2", "ldub", {'l', 'd', 'u', 'b', ' ', 129, ',', '@', '(', 128, ',', 140, ')', }, 0xf0f00000, 0xa0900000, 32 }
+ },
+/* lduh $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "lduh $dr,@$sr", "lduh", "lduh", {'l', 'd', 'u', 'h', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x20b0, 16 }
+ },
+/* lduh $dr,@($sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "lduh $dr,@($sr)", "lduh-2", "lduh", {'l', 'd', 'u', 'h', ' ', 129, ',', '@', '(', 128, ')', }, 0xf0f0, 0x20b0, 16 }
+ },
+/* lduh $dr,@($slo16,$sr) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "lduh $dr,@($slo16,$sr)", "lduh-d", "lduh", {'l', 'd', 'u', 'h', ' ', 129, ',', '@', '(', 140, ',', 128, ')', }, 0xf0f00000, 0xa0b00000, 32 }
+ },
+/* lduh $dr,@($sr,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "lduh $dr,@($sr,$slo16)", "lduh-d2", "lduh", {'l', 'd', 'u', 'h', ' ', 129, ',', '@', '(', 128, ',', 140, ')', }, 0xf0f00000, 0xa0b00000, 32 }
+ },
+/* ld $dr,@$sr+ */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ld $dr,@$sr+", "ld-plus", "ld", {'l', 'd', ' ', 129, ',', '@', 128, '+', }, 0xf0f0, 0x20e0, 16 }
+ },
+/* ld24 $dr,$uimm24 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ld24 $dr,$uimm24", "ld24", "ld24", {'l', 'd', '2', '4', ' ', 129, ',', 142, }, 0xf0000000, 0xe0000000, 32 }
+ },
+/* ldi $dr,$simm8 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldi $dr,$simm8", "ldi8", "ldi", {'l', 'd', 'i', ' ', 129, ',', 134, }, 0xf000, 0x6000, 16 }
+ },
+/* ldi8 $dr,$simm8 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldi8 $dr,$simm8", "ldi8a", "ldi8", {'l', 'd', 'i', '8', ' ', 129, ',', 134, }, 0xf000, 0x6000, 16 }
+ },
+/* ldi $dr,$slo16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "ldi $dr,$slo16", "ldi16", "ldi", {'l', 'd', 'i', ' ', 129, ',', 140, }, 0xf0ff0000, 0x90f00000, 32 }
+ },
+/* ldi16 $dr,$slo16 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "ldi16 $dr,$slo16", "ldi16a", "ldi16", {'l', 'd', 'i', '1', '6', ' ', 129, ',', 140, }, 0xf0ff0000, 0x90f00000, 32 }
+ },
+/* lock $dr,@$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "lock $dr,@$sr", "lock", "lock", {'l', 'o', 'c', 'k', ' ', 129, ',', '@', 128, }, 0xf0f0, 0x20d0, 16 }
+ },
+/* machi $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "machi $src1,$src2", "machi", "machi", {'m', 'a', 'c', 'h', 'i', ' ', 130, ',', 131, }, 0xf0f0, 0x3040, 16 }
+ },
+/* maclo $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "maclo $src1,$src2", "maclo", "maclo", {'m', 'a', 'c', 'l', 'o', ' ', 130, ',', 131, }, 0xf0f0, 0x3050, 16 }
+ },
+/* macwhi $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "macwhi $src1,$src2", "macwhi", "macwhi", {'m', 'a', 'c', 'w', 'h', 'i', ' ', 130, ',', 131, }, 0xf0f0, 0x3060, 16 }
+ },
+/* macwlo $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "macwlo $src1,$src2", "macwlo", "macwlo", {'m', 'a', 'c', 'w', 'l', 'o', ' ', 130, ',', 131, }, 0xf0f0, 0x3070, 16 }
+ },
+/* mul $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mul $dr,$sr", "mul", "mul", {'m', 'u', 'l', ' ', 129, ',', 128, }, 0xf0f0, 0x1060, 16 }
+ },
+/* mulhi $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mulhi $src1,$src2", "mulhi", "mulhi", {'m', 'u', 'l', 'h', 'i', ' ', 130, ',', 131, }, 0xf0f0, 0x3000, 16 }
+ },
+/* mullo $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mullo $src1,$src2", "mullo", "mullo", {'m', 'u', 'l', 'l', 'o', ' ', 130, ',', 131, }, 0xf0f0, 0x3010, 16 }
+ },
+/* mulwhi $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mulwhi $src1,$src2", "mulwhi", "mulwhi", {'m', 'u', 'l', 'w', 'h', 'i', ' ', 130, ',', 131, }, 0xf0f0, 0x3020, 16 }
+ },
+/* mulwlo $src1,$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mulwlo $src1,$src2", "mulwlo", "mulwlo", {'m', 'u', 'l', 'w', 'l', 'o', ' ', 130, ',', 131, }, 0xf0f0, 0x3030, 16 }
+ },
+/* mv $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mv $dr,$sr", "mv", "mv", {'m', 'v', ' ', 129, ',', 128, }, 0xf0f0, 0x1080, 16 }
+ },
+/* mvfachi $dr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvfachi $dr", "mvfachi", "mvfachi", {'m', 'v', 'f', 'a', 'c', 'h', 'i', ' ', 129, }, 0xf0ff, 0x50f0, 16 }
+ },
+/* mvfaclo $dr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvfaclo $dr", "mvfaclo", "mvfaclo", {'m', 'v', 'f', 'a', 'c', 'l', 'o', ' ', 129, }, 0xf0ff, 0x50f1, 16 }
+ },
+/* mvfacmi $dr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvfacmi $dr", "mvfacmi", "mvfacmi", {'m', 'v', 'f', 'a', 'c', 'm', 'i', ' ', 129, }, 0xf0ff, 0x50f2, 16 }
+ },
+/* mvfc $dr,$scr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvfc $dr,$scr", "mvfc", "mvfc", {'m', 'v', 'f', 'c', ' ', 129, ',', 132, }, 0xf0f0, 0x1090, 16 }
+ },
+/* mvtachi $src1 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvtachi $src1", "mvtachi", "mvtachi", {'m', 'v', 't', 'a', 'c', 'h', 'i', ' ', 130, }, 0xf0ff, 0x5070, 16 }
+ },
+/* mvtaclo $src1 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvtaclo $src1", "mvtaclo", "mvtaclo", {'m', 'v', 't', 'a', 'c', 'l', 'o', ' ', 130, }, 0xf0ff, 0x5071, 16 }
+ },
+/* mvtc $sr,$dcr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "mvtc $sr,$dcr", "mvtc", "mvtc", {'m', 'v', 't', 'c', ' ', 128, ',', 133, }, 0xf0f0, 0x10a0, 16 }
+ },
+/* neg $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "neg $dr,$sr", "neg", "neg", {'n', 'e', 'g', ' ', 129, ',', 128, }, 0xf0f0, 0x30, 16 }
+ },
+/* nop */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "nop", "nop", "nop", {'n', 'o', 'p', }, 0xffff, 0x7000, 16 }
+ },
+/* not $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "not $dr,$sr", "not", "not", {'n', 'o', 't', ' ', 129, ',', 128, }, 0xf0f0, 0xb0, 16 }
+ },
+/* rac */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "rac", "rac", "rac", {'r', 'a', 'c', }, 0xffff, 0x5090, 16 }
+ },
+/* rach */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "rach", "rach", "rach", {'r', 'a', 'c', 'h', }, 0xffff, 0x5080, 16 }
+ },
+/* rte */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "rte", "rte", "rte", {'r', 't', 'e', }, 0xffff, 0x10d6, 16 }
+ },
+/* seth $dr,$hi16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "seth $dr,$hi16", "seth", "seth", {'s', 'e', 't', 'h', ' ', 129, ',', 139, }, 0xf0ff0000, 0xd0c00000, 32 }
+ },
+/* sll $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sll $dr,$sr", "sll", "sll", {'s', 'l', 'l', ' ', 129, ',', 128, }, 0xf0f0, 0x1040, 16 }
+ },
+/* sll3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sll3 $dr,$sr,$simm16", "sll3", "sll3", {'s', 'l', 'l', '3', ' ', 129, ',', 128, ',', 135, }, 0xf0f00000, 0x90c00000, 32 }
+ },
+/* slli $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "slli $dr,$uimm5", "slli", "slli", {'s', 'l', 'l', 'i', ' ', 129, ',', 137, }, 0xf0e0, 0x5040, 16 }
+ },
+/* sra $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sra $dr,$sr", "sra", "sra", {'s', 'r', 'a', ' ', 129, ',', 128, }, 0xf0f0, 0x1020, 16 }
+ },
+/* sra3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sra3 $dr,$sr,$simm16", "sra3", "sra3", {'s', 'r', 'a', '3', ' ', 129, ',', 128, ',', 135, }, 0xf0f00000, 0x90a00000, 32 }
+ },
+/* srai $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "srai $dr,$uimm5", "srai", "srai", {'s', 'r', 'a', 'i', ' ', 129, ',', 137, }, 0xf0e0, 0x5020, 16 }
+ },
+/* srl $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "srl $dr,$sr", "srl", "srl", {'s', 'r', 'l', ' ', 129, ',', 128, }, 0xf0f0, 0x1000, 16 }
+ },
+/* srl3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "srl3 $dr,$sr,$simm16", "srl3", "srl3", {'s', 'r', 'l', '3', ' ', 129, ',', 128, ',', 135, }, 0xf0f00000, 0x90800000, 32 }
+ },
+/* srli $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "srli $dr,$uimm5", "srli", "srli", {'s', 'r', 'l', 'i', ' ', 129, ',', 137, }, 0xf0e0, 0x5000, 16 }
+ },
+/* st $src1,@$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "st $src1,@$src2", "st", "st", {'s', 't', ' ', 130, ',', '@', 131, }, 0xf0f0, 0x2040, 16 }
+ },
+/* st $src1,@($src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "st $src1,@($src2)", "st-2", "st", {'s', 't', ' ', 130, ',', '@', '(', 131, ')', }, 0xf0f0, 0x2040, 16 }
+ },
+/* st $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "st $src1,@($slo16,$src2)", "st-d", "st", {'s', 't', ' ', 130, ',', '@', '(', 140, ',', 131, ')', }, 0xf0f00000, 0xa0400000, 32 }
+ },
+/* st $src1,@($src2,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "st $src1,@($src2,$slo16)", "st-d2", "st", {'s', 't', ' ', 130, ',', '@', '(', 131, ',', 140, ')', }, 0xf0f00000, 0xa0400000, 32 }
+ },
+/* stb $src1,@$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "stb $src1,@$src2", "stb", "stb", {'s', 't', 'b', ' ', 130, ',', '@', 131, }, 0xf0f0, 0x2000, 16 }
+ },
+/* stb $src1,@($src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "stb $src1,@($src2)", "stb-2", "stb", {'s', 't', 'b', ' ', 130, ',', '@', '(', 131, ')', }, 0xf0f0, 0x2000, 16 }
+ },
+/* stb $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "stb $src1,@($slo16,$src2)", "stb-d", "stb", {'s', 't', 'b', ' ', 130, ',', '@', '(', 140, ',', 131, ')', }, 0xf0f00000, 0xa0000000, 32 }
+ },
+/* stb $src1,@($src2,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "stb $src1,@($src2,$slo16)", "stb-d2", "stb", {'s', 't', 'b', ' ', 130, ',', '@', '(', 131, ',', 140, ')', }, 0xf0f00000, 0xa0000000, 32 }
+ },
+/* sth $src1,@$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sth $src1,@$src2", "sth", "sth", {'s', 't', 'h', ' ', 130, ',', '@', 131, }, 0xf0f0, 0x2020, 16 }
+ },
+/* sth $src1,@($src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "sth $src1,@($src2)", "sth-2", "sth", {'s', 't', 'h', ' ', 130, ',', '@', '(', 131, ')', }, 0xf0f0, 0x2020, 16 }
+ },
+/* sth $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sth $src1,@($slo16,$src2)", "sth-d", "sth", {'s', 't', 'h', ' ', 130, ',', '@', '(', 140, ',', 131, ')', }, 0xf0f00000, 0xa0200000, 32 }
+ },
+/* sth $src1,@($src2,$slo16) */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "sth $src1,@($src2,$slo16)", "sth-d2", "sth", {'s', 't', 'h', ' ', 130, ',', '@', '(', 131, ',', 140, ')', }, 0xf0f00000, 0xa0200000, 32 }
+ },
+/* st $src1,@+$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "st $src1,@+$src2", "st-plus", "st", {'s', 't', ' ', 130, ',', '@', '+', 131, }, 0xf0f0, 0x2060, 16 }
+ },
+/* st $src1,@-$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "st $src1,@-$src2", "st-minus", "st", {'s', 't', ' ', 130, ',', '@', '-', 131, }, 0xf0f0, 0x2070, 16 }
+ },
+/* sub $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "sub $dr,$sr", "sub", "sub", {'s', 'u', 'b', ' ', 129, ',', 128, }, 0xf0f0, 0x20, 16 }
+ },
+/* subv $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "subv $dr,$sr", "subv", "subv", {'s', 'u', 'b', 'v', ' ', 129, ',', 128, }, 0xf0f0, 0x0, 16 }
+ },
+/* subx $dr,$sr */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "subx $dr,$sr", "subx", "subx", {'s', 'u', 'b', 'x', ' ', 129, ',', 128, }, 0xf0f0, 0x10, 16 }
+ },
+/* trap $uimm4 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_FILL_SLOT)|(1<<CGEN_INSN_UNCOND_CTI), { 0 } } },
+ { "trap $uimm4", "trap", "trap", {'t', 'r', 'a', 'p', ' ', 136, }, 0xfff0, 0x10f0, 16 }
+ },
+/* unlock $src1,@$src2 */
+ {
+ { 1, 1, 1, 1, { 0, 0, { 0 } } },
+ { "unlock $src1,@$src2", "unlock", "unlock", {'u', 'n', 'l', 'o', 'c', 'k', ' ', 130, ',', '@', 131, }, 0xf0f0, 0x2050, 16 }
+ },
+/* push $src1 */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "push $src1", "push", "push", {'p', 'u', 's', 'h', ' ', 130, }, 0xf0ff, 0x207f, 16 }
+ },
+/* pop $dr */
+ {
+ { 1, 1, 1, 1, { 0, 0|(1<<CGEN_INSN_ALIAS), { 0 } } },
+ { "pop $dr", "pop", "pop", {'p', 'o', 'p', ' ', 129, }, 0xf0ff, 0x20ef, 16 }
+ },
+};
+
+CGEN_INSN_TABLE m32r_cgen_insn_table = {
+ & m32r_cgen_insn_table_entries[0],
+ CGEN_NUM_INSNS,
+ NULL,
+ m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
+ m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
+};
+
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+unsigned int
+m32r_cgen_asm_hash_insn (insn)
+ const char *insn;
+{
+ return CGEN_ASM_HASH (insn);
+}
+
+unsigned int
+m32r_cgen_dis_hash_insn (buf, value)
+ const char *buf;
+ unsigned long value;
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+CGEN_OPCODE_DATA m32r_cgen_opcode_data = {
+ & m32r_cgen_hw_entries[0],
+ & m32r_cgen_insn_table,
+};
+
+void
+m32r_cgen_init_tables (mach)
+ int mach;
+{
+}
+
+/* Main entry point for stuffing values in cgen_fields. */
+
+CGEN_INLINE void
+m32r_cgen_set_operand (opindex, valuep, fields)
+ int opindex;
+ const long *valuep;
+ struct cgen_fields *fields;
+{
+ switch (opindex)
+ {
+ case 0 :
+ fields->f_r2 = *valuep;
+ break;
+ case 1 :
+ fields->f_r1 = *valuep;
+ break;
+ case 2 :
+ fields->f_r1 = *valuep;
+ break;
+ case 3 :
+ fields->f_r2 = *valuep;
+ break;
+ case 4 :
+ fields->f_r2 = *valuep;
+ break;
+ case 5 :
+ fields->f_r1 = *valuep;
+ break;
+ case 6 :
+ fields->f_simm8 = *valuep;
+ break;
+ case 7 :
+ fields->f_simm16 = *valuep;
+ break;
+ case 8 :
+ fields->f_uimm4 = *valuep;
+ break;
+ case 9 :
+ fields->f_uimm5 = *valuep;
+ break;
+ case 10 :
+ fields->f_uimm16 = *valuep;
+ break;
+ case 11 :
+ fields->f_hi16 = *valuep;
+ break;
+ case 12 :
+ fields->f_simm16 = *valuep;
+ break;
+ case 13 :
+ fields->f_uimm16 = *valuep;
+ break;
+ case 14 :
+ fields->f_uimm24 = *valuep;
+ break;
+ case 15 :
+ fields->f_disp8 = *valuep;
+ break;
+ case 16 :
+ fields->f_disp16 = *valuep;
+ break;
+ case 17 :
+ fields->f_disp24 = *valuep;
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while setting operand.\n",
+ opindex);
+ abort ();
+ }
+}
+
+/* Main entry point for getting values from cgen_fields. */
+
+CGEN_INLINE long
+m32r_cgen_get_operand (opindex, fields)
+ int opindex;
+ const struct cgen_fields *fields;
+{
+ long value;
+
+ switch (opindex)
+ {
+ case 0 :
+ value = fields->f_r2;
+ break;
+ case 1 :
+ value = fields->f_r1;
+ break;
+ case 2 :
+ value = fields->f_r1;
+ break;
+ case 3 :
+ value = fields->f_r2;
+ break;
+ case 4 :
+ value = fields->f_r2;
+ break;
+ case 5 :
+ value = fields->f_r1;
+ break;
+ case 6 :
+ value = fields->f_simm8;
+ break;
+ case 7 :
+ value = fields->f_simm16;
+ break;
+ case 8 :
+ value = fields->f_uimm4;
+ break;
+ case 9 :
+ value = fields->f_uimm5;
+ break;
+ case 10 :
+ value = fields->f_uimm16;
+ break;
+ case 11 :
+ value = fields->f_hi16;
+ break;
+ case 12 :
+ value = fields->f_simm16;
+ break;
+ case 13 :
+ value = fields->f_uimm16;
+ break;
+ case 14 :
+ value = fields->f_uimm24;
+ break;
+ case 15 :
+ value = fields->f_disp8;
+ break;
+ case 16 :
+ value = fields->f_disp16;
+ break;
+ case 17 :
+ value = fields->f_disp24;
+ break;
+
+ default :
+ fprintf (stderr, "Unrecognized field %d while getting operand.\n",
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
projects / external / binutils.git / commitdiff