return ret;
}
+ platform_set_drvdata(pdev, dra7xx);
+
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
if (ret < 0)
goto err_gpio;
- platform_set_drvdata(pdev, dra7xx);
return 0;
err_gpio:
goto fail_bus_clk;
}
+ platform_set_drvdata(pdev, exynos_pcie);
+
ret = exynos_add_pcie_port(exynos_pcie, pdev);
if (ret < 0)
goto fail_bus_clk;
- platform_set_drvdata(pdev, exynos_pcie);
return 0;
fail_bus_clk:
if (ret)
imx6_pcie->link_gen = 1;
+ platform_set_drvdata(pdev, imx6_pcie);
+
ret = imx6_add_pcie_port(imx6_pcie, pdev);
if (ret < 0)
return ret;
- platform_set_drvdata(pdev, imx6_pcie);
return 0;
}
if (ret)
return ret;
+ platform_set_drvdata(pdev, ks_pcie);
+
ret = ks_add_pcie_port(ks_pcie, pdev);
if (ret < 0)
goto fail_clk;
if (!ls_pcie_is_bridge(pcie))
return -ENODEV;
+ platform_set_drvdata(pdev, pcie);
+
ret = ls_add_pcie_port(pcie);
if (ret < 0)
return ret;
goto fail;
}
+ platform_set_drvdata(pdev, pcie);
+
ret = armada8k_add_pcie_port(pcie, pdev);
if (ret)
goto fail;
if (IS_ERR(artpec6_pcie->regmap))
return PTR_ERR(artpec6_pcie->regmap);
+ platform_set_drvdata(pdev, artpec6_pcie);
+
ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
if (ret < 0)
return ret;
if (IS_ERR(pp->dbi_base))
return PTR_ERR(pp->dbi_base);
+ platform_set_drvdata(pdev, dw_plat_pcie);
+
ret = dw_plat_add_pcie_port(pp, pdev);
if (ret < 0)
return ret;
if (IS_ERR(pp->dbi_base))
return PTR_ERR(pp->dbi_base);
+ platform_set_drvdata(pdev, hisi_pcie);
+
ret = hisi_add_pcie_port(hisi_pcie, pdev);
if (ret)
return ret;
if (ret)
return ret;
+ platform_set_drvdata(pdev, pcie);
+
ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(dev, "cannot initialize host\n");
if (of_property_read_bool(np, "st,pcie-is-gen1"))
spear13xx_pcie->is_gen1 = true;
+ platform_set_drvdata(pdev, spear13xx_pcie);
+
ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
if (ret < 0)
goto fail_clk;
- platform_set_drvdata(pdev, spear13xx_pcie);
return 0;
fail_clk: