struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen;
const struct brw_compiler *compiler = screen->compiler;
const struct nir_shader_compiler_options *options =
- compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].NirOptions;
+ compiler->nir_options[MESA_SHADER_TESS_CTRL];
void *mem_ctx = ralloc_context(NULL);
struct brw_tcs_prog_data *tcs_prog_data =
rzalloc(mem_ctx, struct brw_tcs_prog_data);
gl_shader_stage stage = stage_from_pipe(pstage);
assert(ir == PIPE_SHADER_IR_NIR);
- return screen->compiler->glsl_compiler_options[stage].NirOptions;
+ return screen->compiler->nir_options[stage];
}
static struct disk_cache *
{
const struct brw_compiler *compiler = screen->compiler;
const struct nir_shader_compiler_options *options =
- compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].NirOptions;
+ compiler->nir_options[MESA_SHADER_TESS_CTRL];
void *mem_ctx = ralloc_context(NULL);
struct brw_tcs_prog_data *tcs_prog_data =
rzalloc(mem_ctx, struct brw_tcs_prog_data);
struct iris_screen *screen = (void *) ctx->screen;
struct u_upload_mgr *uploader = ice->shaders.uploader_unsync;
const nir_shader_compiler_options *options =
- screen->compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
+ screen->compiler->nir_options[MESA_SHADER_COMPUTE];
nir_shader *nir;
switch (state->ir_type) {
gl_shader_stage stage = stage_from_pipe(pstage);
assert(ir == PIPE_SHADER_IR_NIR);
- return screen->compiler->glsl_compiler_options[stage].NirOptions;
+ return screen->compiler->nir_options[stage];
}
static struct disk_cache *
{
const struct brw_compiler *compiler = blorp->compiler;
- nir->options =
- compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
+ nir->options = compiler->nir_options[MESA_SHADER_FRAGMENT];
memset(wm_prog_data, 0, sizeof(*wm_prog_data));
{
const struct brw_compiler *compiler = blorp->compiler;
- nir->options =
- compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
+ nir->options = compiler->nir_options[MESA_SHADER_VERTEX];
brw_preprocess_nir(compiler, nir, NULL);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
{
const struct brw_compiler *compiler = blorp->compiler;
- nir->options =
- compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
+ nir->options = compiler->nir_options[MESA_SHADER_COMPUTE];
memset(cs_prog_data, 0, sizeof(*cs_prog_data));
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
- compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
- compiler->glsl_compiler_options[i].MaxIfDepth =
- devinfo->ver < 6 ? 16 : UINT_MAX;
-
- /* We handle this in NIR */
- compiler->glsl_compiler_options[i].EmitNoIndirectInput = false;
- compiler->glsl_compiler_options[i].EmitNoIndirectOutput = false;
- compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
- compiler->glsl_compiler_options[i].EmitNoIndirectTemp = false;
-
- bool is_scalar = compiler->scalar_stage[i];
- compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
-
struct nir_shader_compiler_options *nir_options =
rzalloc(compiler, struct nir_shader_compiler_options);
+ bool is_scalar = compiler->scalar_stage[i];
if (is_scalar) {
*nir_options = scalar_nir_options;
} else {
nir_options->force_indirect_unrolling |=
brw_nir_no_indirect_mask(compiler, i);
- compiler->glsl_compiler_options[i].NirOptions = nir_options;
-
- compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
+ compiler->nir_options[i] = nir_options;
}
return compiler;
struct nir_shader;
struct brw_program;
+struct nir_shader_compiler_options;
typedef struct nir_shader nir_shader;
struct brw_compiler {
bool scalar_stage[MESA_ALL_SHADER_STAGES];
bool use_tcs_8_patch;
- struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
+ struct nir_shader_compiler_options *nir_options[MESA_ALL_SHADER_STAGES];
/**
* Apply workarounds for SIN and COS output range problems.
void *mem_ctx)
{
const nir_shader_compiler_options *nir_options =
- compiler->glsl_compiler_options[MESA_SHADER_CALLABLE].NirOptions;
+ compiler->nir_options[MESA_SHADER_CALLABLE];
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE,
nir_options,
{
const struct intel_device_info *devinfo = compiler->devinfo;
const nir_shader_compiler_options *nir_options =
- compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;
+ compiler->nir_options[MESA_SHADER_COMPUTE];
STATIC_ASSERT(sizeof(struct brw_rt_raygen_trampoline_params) == 32);
const struct anv_physical_device *pdevice = device->physical;
const struct brw_compiler *compiler = pdevice->compiler;
const nir_shader_compiler_options *nir_options =
- compiler->glsl_compiler_options[stage].NirOptions;
+ compiler->nir_options[stage];
uint32_t *spirv = (uint32_t *) module->data;
assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
const struct brw_compiler *compiler =
pipeline->device->physical->compiler;
const nir_shader_compiler_options *nir_options =
- compiler->glsl_compiler_options[stage->stage].NirOptions;
+ compiler->nir_options[stage->stage];
nir_shader *nir;
nir = anv_device_search_for_nir(pipeline->device, cache,
anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
- if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
+ if (prev_stage && compiler->nir_options[s]->unify_interfaces) {
prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &