AMDGPU::FLAT_SCR_HI)
.addReg(FlatScrInitLo, RegState::Kill)
.addImm(8);
- LShr->getOperand(3).setIsDead(true); // Mark SCC as dead.
+ LShr->getOperand(3).setIsDead(); // Mark SCC as dead.
}
// Note SGPRSpill stack IDs should only be used for SGPR spilling to VGPRs, not
const DebugLoc &DL = MI.getDebugLoc();
MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
.add(MI.getOperand(0));
- Br->getOperand(1).setIsUndef(true); // read undef SCC
+ Br->getOperand(1).setIsUndef(); // read undef SCC
MI.eraseFromParent();
return BB;
}
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitDefine);
- I->getOperand(2).setIsDead(true); // Mark SCC as dead.
+ I->getOperand(2).setIsDead(); // Mark SCC as dead.
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
}
}
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitKill);
- I->getOperand(2).setIsDead(true); // Mark SCC as dead.
+ I->getOperand(2).setIsDead(); // Mark SCC as dead.
// Restore active lanes
if (TmpVGPRLive)
Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR);
FIOp.setReg(TmpReg);
- FIOp.setIsKill(true);
+ FIOp.setIsKill();
if ((!FrameReg || !Offset) && TmpReg) {
unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
.addImm(ST.getWavefrontSizeLog2())
.addReg(FrameReg);
if (IsSALU && !LiveSCC)
- Shift.getInstr()->getOperand(3).setIsDead(
- true); // Mark SCC as dead.
+ Shift.getInstr()->getOperand(3).setIsDead(); // Mark SCC as dead.
if (IsSALU && LiveSCC) {
Register NewDest =
RS->scavengeRegister(&AMDGPU::SReg_32RegClass, Shift, 0);