intel/compiler: fix generation of vec8/vec16 alu instruction

I stumbled on this when I inserted some suboptimal lowering code after all
optimizations. Adding certain subset of optimizations after my lowering code
actually avoided this bug, so I think it's not possible to hit this on upstream.

Let's fix this for the next person generating suboptimal code...

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20857>

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index bed647e..8da05b8 100644 (file)
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1019,7 +1019,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
          }
       }
 
-      for (unsigned i = 0; i < 4; i++) {
+      unsigned last_bit = util_last_bit(instr->dest.write_mask);
+
+      for (unsigned i = 0; i < last_bit; i++) {
          if (!(instr->dest.write_mask & (1 << i)))
             continue;
 
@@ -1037,7 +1039,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
        * any swizzling.
        */
       if (need_extra_copy) {
-         for (unsigned i = 0; i < 4; i++) {
+         for (unsigned i = 0; i < last_bit; i++) {
             if (!(instr->dest.write_mask & (1 << i)))
                continue;