x86: drop redundant VSIB handling code

The vecsib && !base_reg case is already being handled (in a more correct
manner) by earlier code.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c002807..d871aa3 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 
+       * config/tc-i386.c (build_modrm_byte): Drop VSIB handling from
+       code also setting fake_zero_displacement.
+
+2017-11-23  Jan Beulich  <jbeulich@suse.com>
+
        * testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0.
        * testsuite/gas/i386/intel.s: Test ud2 instead of ud2b.
        * testsuite/gas/i386/opcode.s: Likewise.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5a7066c..e22e74c 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6591,13 +6591,7 @@ build_modrm_byte (void)
            {
              i.rm.mode = 0;
              if (!i.disp_operands)
-               {
-                 fake_zero_displacement = 1;
-                 /* Instructions with VSIB byte need 32bit displacement
-                    if there is no base register.  */
-                 if (i.tm.opcode_modifier.vecsib)
-                   i.types[op].bitfield.disp32 = 1;
-               }
+               fake_zero_displacement = 1;
              if (i.index_reg == 0)
                {
                  gas_assert (!i.tm.opcode_modifier.vecsib);