if (zs->streamout.so_info_slots)
streamout = &zs->streamout;
- nir = nir_shader_clone(NULL, zs->nir);
- NIR_PASS_V(nir, nir_lower_clip_halfz);
+ if (!zink_vs_key(key)->clip_halfz) {
+ nir = nir_shader_clone(NULL, zs->nir);
+ NIR_PASS_V(nir, nir_lower_clip_halfz);
+ }
}
} else {
if (!zink_fs_key(key)->samples &&
struct zink_gfx_program *curr_program;
unsigned dirty_shader_stages : 6; /* mask of changed shader stages */
+ bool last_vertex_stage_dirty;
struct hash_table *render_pass_cache;
static struct zink_gfx_program *
get_gfx_program(struct zink_context *ctx)
{
+ if (ctx->last_vertex_stage_dirty) {
+ if (ctx->gfx_stages[PIPE_SHADER_GEOMETRY])
+ ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_GEOMETRY);
+ else if (ctx->gfx_stages[PIPE_SHADER_TESS_EVAL])
+ ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_TESS_EVAL);
+ else
+ ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_VERTEX);
+ }
if (ctx->dirty_shader_stages) {
struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
ctx->gfx_stages);
zink_bind_rasterizer_state(struct pipe_context *pctx, void *cso)
{
struct zink_context *ctx = zink_context(pctx);
+ bool clip_halfz = ctx->rast_state ? ctx->rast_state->base.clip_halfz : false;
ctx->rast_state = cso;
if (ctx->rast_state) {
ctx->gfx_pipeline_state.dirty = true;
}
+ if (clip_halfz != ctx->rast_state->base.clip_halfz)
+ ctx->last_vertex_stage_dirty = true;
+
if (ctx->line_width != ctx->rast_state->line_width) {
ctx->line_width = ctx->rast_state->line_width;
ctx->gfx_pipeline_state.dirty = true;