brw_program_append_entry(p, list_entry);
}
-static void brw_program_add_relocatable(struct brw_program *p,
- struct brw_program_instruction *reloc)
+static void
+brw_program_add_relocatable(struct brw_program *p,
+ struct brw_program_instruction *instruction)
{
struct brw_program_instruction *list_entry;
list_entry = calloc(sizeof(struct brw_program_instruction), 1);
list_entry->type = GEN4ASM_INSTRUCTION_GEN_RELOCATABLE;
- list_entry->insn.reloc = reloc->insn.reloc;
+ list_entry->insn.gen = instruction->insn.gen;
+ list_entry->reloc = instruction->reloc;
brw_program_append_entry(p, list_entry);
}
memset(&$$, 0, sizeof($$));
GEN(&$$)->header.opcode = $1;
GEN(&$$)->header.execution_size = $2;
- $$.insn.reloc.first_reloc_target = $3.reloc_target;
- $$.insn.reloc.first_reloc_offset = $3.imm32;
+ $$.reloc.first_reloc_target = $3.reloc_target;
+ $$.reloc.first_reloc_offset = $3.imm32;
}
| ELSE execsize relativelocation instoptions
{
set_instruction_dest(&$$, &ip_dst);
set_instruction_src0(&$$, &ip_src, NULL);
set_instruction_src1(&$$, &$3, NULL);
- $$.insn.reloc.first_reloc_target = $3.reloc_target;
- $$.insn.reloc.first_reloc_offset = $3.imm32;
+ $$.reloc.first_reloc_target = $3.reloc_target;
+ $$.reloc.first_reloc_offset = $3.imm32;
} else if(IS_GENp(6)) {
memset(&$$, 0, sizeof($$));
GEN(&$$)->header.opcode = $1;
GEN(&$$)->header.execution_size = $2;
- $$.insn.reloc.first_reloc_target = $3.reloc_target;
- $$.insn.reloc.first_reloc_offset = $3.imm32;
+ $$.reloc.first_reloc_target = $3.reloc_target;
+ $$.reloc.first_reloc_offset = $3.imm32;
} else {
error(&@1, "'ELSE' instruction is not implemented.\n");
}
set_instruction_src0(&$$, &ip_src, NULL);
set_instruction_src1(&$$, &$4, NULL);
}
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
}
| predicate IF execsize relativelocation relativelocation
{
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
GEN(&$$)->header.execution_size = $3;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
- $$.insn.reloc.second_reloc_target = $5.reloc_target;
- $$.insn.reloc.second_reloc_offset = $5.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.second_reloc_target = $5.reloc_target;
+ $$.reloc.second_reloc_offset = $5.imm32;
}
;
GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
set_instruction_src0(&$$, &ip_src, NULL);
set_instruction_src1(&$$, &$4, NULL);
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
} else if (IS_GENp(6)) {
/* Gen6 spec:
dest must have the same element size as src0.
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
GEN(&$$)->header.execution_size = $3;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
} else {
error(&@2, "'WHILE' instruction is not implemented!\n");
}
memset(&$$, 0, sizeof($$));
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
- $$.insn.reloc.second_reloc_target = $5.reloc_target;
- $$.insn.reloc.second_reloc_offset = $5.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.second_reloc_target = $5.reloc_target;
+ $$.reloc.second_reloc_offset = $5.imm32;
dst_null_reg.width = $3;
set_instruction_dest(&$$, &dst_null_reg);
set_instruction_src0(&$$, &src_null_reg, NULL);
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
dst_null_reg.width = $3;
set_instruction_dest(&$$, &dst_null_reg);
}
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
- $$.insn.reloc.second_reloc_target = $5.reloc_target;
- $$.insn.reloc.second_reloc_offset = $5.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.second_reloc_target = $5.reloc_target;
+ $$.reloc.second_reloc_offset = $5.imm32;
dst_null_reg.width = $3;
set_instruction_dest(&$$, &dst_null_reg);
set_instruction_src0(&$$, &src_null_reg, NULL);
src0.reg.vstride = 2; /*encoded 2*/
set_instruction_src0(&$$, &src0, NULL);
- $$.insn.reloc.first_reloc_target = $5.reloc_target;
- $$.insn.reloc.first_reloc_offset = $5.imm32;
+ $$.reloc.first_reloc_target = $5.reloc_target;
+ $$.reloc.first_reloc_offset = $5.imm32;
}
| predicate RET execsize dstoperandex src instoptions
{
set_instruction_dest(&$$, &ip_dst);
set_instruction_src0(&$$, &ip_src, NULL);
set_instruction_src1(&$$, &$4, NULL);
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
}
;
set_instruction_predicate(&$$, &$1);
GEN(&$$)->header.opcode = $2;
GEN(&$$)->header.execution_size = $3;
- $$.insn.reloc.first_reloc_target = $4.reloc_target;
- $$.insn.reloc.first_reloc_offset = $4.imm32;
- $$.insn.reloc.second_reloc_target = $5.reloc_target;
- $$.insn.reloc.second_reloc_offset = $5.imm32;
+ $$.reloc.first_reloc_target = $4.reloc_target;
+ $$.reloc.first_reloc_offset = $4.imm32;
+ $$.reloc.second_reloc_target = $5.reloc_target;
+ $$.reloc.second_reloc_offset = $5.imm32;
}
;