media: atomisp: fix clock rate frequency setting

changeset d5426f4c2eba ("media: staging: atomisp: use clock framework for camera clocks")
removed a platform-specific code to set the clock rate, in favor of
using the Kernel clock framework.

However, instead of passing the frequency for clk_set_rate(),
it is passing either 0 or 1.

Looking at the original patchset, it seems that there are two
possible configurations for the ISP:

	0 - it will use a 25 MHz XTAL to provide the clock;
	1 - it will use a PLL with is set to 19.2 MHz
	    (only for the CHT version?)

Eventually, different XTALs and/or PLL frequencies might
be possible some day, so, re-implent the logic for it to be
more generic.

Fixes: d5426f4c2eba ("media: staging: atomisp: use clock framework for camera clocks")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c
index 783ea48b26fb80925d8105b8812f7393d19427f3..bdb4fdebacf55d49118182635f3647b280ffc901 100644 (file)
--- a/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c
+++ b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c
@@ -17,7 +17,15 @@
 
 #define MAX_SUBDEVS 8
 
-#define VLV2_CLK_PLL_19P2MHZ 1 /* XTAL on CHT */
+
+enum clock_rate {
+       VLV2_CLK_XTAL_25_0MHz = 0,
+       VLV2_CLK_PLL_19P2MHZ = 1
+};
+
+#define CLK_RATE_19_2MHZ       19200000
+#define CLK_RATE_25_0MHZ       25000000
+
 #define ELDO1_SEL_REG  0x19
 #define ELDO1_1P8V     0x16
 #define ELDO1_CTRL_SHIFT 0x00
@@ -28,7 +36,7 @@
 struct gmin_subdev {
        struct v4l2_subdev *subdev;
        int clock_num;
-       int clock_src;
+       enum clock_rate clock_src;
        bool clock_on;
        struct clk *pmc_clk;
        struct gpio_desc *gpio0;
@@ -570,7 +578,7 @@ static int gmin_flisclk_ctrl(struct v4l2_subdev *subdev, int on)
                return 0;
 
        if (on) {
-               ret = clk_set_rate(gs->pmc_clk, gs->clock_src);
+               ret = clk_set_rate(gs->pmc_clk, gs->clock_src ? CLK_RATE_19_2MHZ : CLK_RATE_25_0MHZ);
 
                if (ret)
                        dev_err(&client->dev, "unable to set PMC rate %d\n",