drm/i915/dg2: Drop 38.4 MHz MPLLB tables

Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-2-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 4cdce01..7e6245b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -251,197 +251,6 @@ static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
 };
 
 /*
- * Basic DP link rates with 38.4 MHz reference clock.
- */
-
-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
-       .clock = 162000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
-       .clock = 270000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
-       .clock = 540000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
-       .clock = 810000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
-       .clock = 1000000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
-
-       /*
-        * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-        */
-       .mpllb_sscen =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
-       .mpllb_sscstep =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
-       .clock = 1350000,
-       .ref_control =
-               REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-       .mpllb_cp =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-       .mpllb_div =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
-       .mpllb_div2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
-       .mpllb_fracn1 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-       .mpllb_fracn2 =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
-
-       /*
-        * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-        */
-       .mpllb_sscen =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
-       .mpllb_sscstep =
-               REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
-};
-
-static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
-       &dg2_dp_rbr_38_4,
-       &dg2_dp_hbr1_38_4,
-       &dg2_dp_hbr2_38_4,
-       &dg2_dp_hbr3_38_4,
-       &dg2_dp_uhbr10_38_4,
-       &dg2_dp_uhbr13_38_4,
-       NULL,
-};
-
-/*
  * eDP link rates with 100 MHz reference clock.
  */
 
@@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
                return dg2_edp_tables;
        } else if (intel_crtc_has_dp_encoder(crtc_state)) {
-               /*
-                * FIXME: Initially we're just enabling the "combo" outputs on
-                * port A-D.  The MPLLB for those ports takes an input from the
-                * "Display Filter PLL" which always has an output frequency
-                * of 100 MHz, hence the use of the _100 tables below.
-                *
-                * Once we enable port TC1 it will either use the same 100 MHz
-                * "Display Filter PLL" (when strapped to support a native
-                * display connection) or different 38.4 MHz "Filter PLL" when
-                * strapped to support a USB connection, so we'll need to check
-                * that to determine which table to use.
-                */
-               if (0)
-                       return dg2_dp_38_4_tables;
-               else
-                       return dg2_dp_100_tables;
+               return dg2_dp_100_tables;
        } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
                return dg2_hdmi_tables;
        }