drm/amdgpu: fix several indentation issues
authorColin Ian King <colin.king@canonical.com>
Tue, 12 Feb 2019 14:05:08 +0000 (14:05 +0000)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 13 Feb 2019 22:51:37 +0000 (17:51 -0500)
There are several statements that are incorrectly indented. Fix these.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

index bc62bf4..b65e181 100644 (file)
@@ -207,7 +207,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
        if (!r) {
                acpi_status = amdgpu_acpi_init(adev);
                if (acpi_status)
-               dev_dbg(&dev->pdev->dev,
+                       dev_dbg(&dev->pdev->dev,
                                "Error during ACPI methods call\n");
        }
 
index db443ec..bea32f0 100644 (file)
@@ -2980,7 +2980,7 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
                                 struct amdgpu_irq_src *source,
                                 struct amdgpu_iv_entry *entry)
 {
-               unsigned long flags;
+       unsigned long flags;
        unsigned crtc_id;
        struct amdgpu_crtc *amdgpu_crtc;
        struct amdgpu_flip_work *works;
index e347b40..727370c 100644 (file)
@@ -32,7 +32,7 @@
 
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
-    u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+       u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
        tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
        tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
index 79c1a9b..9d8df68 100644 (file)
@@ -1436,7 +1436,7 @@ static int si_common_early_init(void *handle)
                        AMD_CG_SUPPORT_UVD_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_HDP_MGCG;
-                       adev->pg_flags = 0;
+               adev->pg_flags = 0;
                adev->external_rev_id = (adev->rev_id == 0) ? 1 :
                                        (adev->rev_id == 1) ? 5 : 6;
                break;
index d138dda..58f5589 100644 (file)
@@ -1211,7 +1211,7 @@ int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
                                hwmgr->platform_descriptor.TDPAdjustment :
                                (-1 * hwmgr->platform_descriptor.TDPAdjustment);
 
-                if (hwmgr->chip_id > CHIP_TONGA)
+               if (hwmgr->chip_id > CHIP_TONGA)
                        target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
                else
                        target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100;
index 0769b1e..aad79af 100644 (file)
@@ -3456,7 +3456,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
        disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
                            !hwmgr->display_config->multi_monitor_in_sync) ||
                             vblank_too_short;
-    latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
+       latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
 
        /* gfxclk */
        dpm_table = &(data->dpm_table.gfx_table);