drm/amd/display: Fix OPTC_DATA_FORMAT programming

This should be programmed with timing rather than with odm.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 2972392..800be26 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -288,6 +288,17 @@ void optc1_program_timing(
        if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
                h_div = H_TIMING_DIV_BY2;
 
+       if (REG(OPTC_DATA_FORMAT_CONTROL)) {
+               uint32_t data_fmt = 0;
+
+               if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                       data_fmt = 1;
+               else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                       data_fmt = 2;
+
+               REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
+       }
+
 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
        if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
                if (optc1->opp_count == 4)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 8c16967..d8b18c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -239,7 +239,6 @@ void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c
        int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
                        / opp_cnt;
        uint32_t memory_mask;
-       uint32_t data_fmt = 0;
 
        ASSERT(opp_cnt == 2);
 
@@ -262,13 +261,6 @@ void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c
                REG_SET(OPTC_MEMORY_CONFIG, 0,
                        OPTC_MEM_SEL, memory_mask);
 
-       if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
-               data_fmt = 1;
-       else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-               data_fmt = 2;
-
-       REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
-
        REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
                        OPTC_NUM_OF_INPUT_SEGMENT, 1,
                        OPTC_SEG0_SRC_SEL, opp_id[0],

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 6d13431..b1f228f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -209,7 +209,6 @@ static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, in
        int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
                        / opp_cnt;
        uint32_t memory_mask = 0;
-       uint32_t data_fmt = 0;
 
        /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
         * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
@@ -240,13 +239,6 @@ static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, in
                REG_SET(OPTC_MEMORY_CONFIG, 0,
                        OPTC_MEM_SEL, memory_mask);
 
-       if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
-               data_fmt = 1;
-       else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-               data_fmt = 2;
-
-       REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
-
        if (opp_cnt == 2) {
                REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
                                OPTC_NUM_OF_INPUT_SEGMENT, 1,