mmc: omap_hsmmc: Enable DDR mode support

In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 507435a11f3f990a2784c92531c55ed4f6be1489..6aca9e90cfde823c9e789d93a2c6fcc44c231c82 100644 (file)
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -89,6 +89,7 @@ struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH                 (0x0 << 8)
 #define RESERVED_MASK                  (0x3 << 9)
 #define CTPL_MMC_SD                    (0x0 << 11)
+#define DDR                            (0x1 << 19)
 #define DMA_MASTER                     (0x1 << 20)
 #define BLEN_512BYTESLEN               (0x200 << 0)
 #define NBLK_STPCNT                    (0x0 << 16)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index c6b74a1263f73910f0ed3568c777579953ecb0fa..2f4909e34bd69a0dc764c1d041a6bfababa033f8 100644 (file)
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
        val &= ~AC12_UHSMC_MASK;
        priv->mode = mmc->selected_mode;
 
+       if (mmc_is_mode_ddr(priv->mode))
+               writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
+       else
+               writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
+
        switch (priv->mode) {
        case MMC_HS_200:
        case UHS_SDR104: