unsigned int t_clk;
int extended_rx_coal_limit;
int tx_bw_control;
+ int tx_csum_limit;
};
#define TX_BW_CONTROL_ABSENT 0
l4i_chk = 0;
if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ int hdr_len;
int tag_bytes;
BUG_ON(skb->protocol != htons(ETH_P_IP) &&
skb->protocol != htons(ETH_P_8021Q));
- tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
- if (unlikely(tag_bytes & ~12)) {
+ hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
+ tag_bytes = hdr_len - ETH_HLEN;
+ if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
+ unlikely(tag_bytes & ~12)) {
if (skb_checksum_help(skb) == 0)
goto no_csum;
kfree_skb(skb);
* Detect hardware parameters.
*/
msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+ msp->tx_csum_limit = pd->tx_csum_limit ? pd->tx_csum_limit : 9 * 1024;
infer_hw_params(msp);
platform_set_drvdata(pdev, msp);
struct mbus_dram_target_info *dram;
struct platform_device *shared_smi;
unsigned int t_clk;
+ /*
+ * Max packet size for Tx IP/Layer 4 checksum, when set to 0, default
+ * limit of 9KiB will be used.
+ */
+ int tx_csum_limit;
};
#define MV643XX_ETH_PHY_ADDR_DEFAULT 0