drm/amd/display: Update Z8 SR exit/enter latencies

[Why]
Request from HW team to update the latencies to the new measured values.

[How]
Update the values in the bounding box.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index a86a3a9..acda3e1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -149,8 +149,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
        .num_states = 5,
        .sr_exit_time_us = 16.5,
        .sr_enter_plus_exit_time_us = 18.5,
-       .sr_exit_z8_time_us = 280.0,
-       .sr_enter_plus_exit_z8_time_us = 350.0,
+       .sr_exit_z8_time_us = 210.0,
+       .sr_enter_plus_exit_z8_time_us = 310.0,
        .writeback_latency_us = 12.0,
        .dram_channel_width_bytes = 4,
        .round_trip_ping_latency_dcfclk_cycles = 106,